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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Chunlin Liang — 32 Patents

Intel: 32 patents #1,151 of 30,777Top 4%
San Jose, CA: #1,882 of 32,062 inventorsTop 6%
California: #15,919 of 386,348 inventorsTop 5%
Overall (All Time): #110,428 of 4,157,543Top 3%
32 Patents All Time
Chunlin Liang has been granted 32 US patents while listed as an inventor at Intel. The first was granted in 1999 and the most recent in May 2007. Chunlin Liang ranks #110,428 of 4,157,543 US inventors in our database (top 2.7%). Patent records list Chunlin Liang in San Jose, CA, US.

Patents per Year

Patents granted per year, 1999 to 2007Bar chart with a peak of 5 patents in 2002.peak 51999: 2 patents19992000: 4 patents20002001: 4 patents20012002: 5 patents20022003: 5 patents20032004: 5 patents20042005: 1 patents20052006: 4 patents20062007: 2 patents2007

Issued Patents All Time

Showing 1–25 of 32 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
7223992 Thermal conducting trench in a semiconductor structure Brian S. Doyle 2007-05-29 $13,871,000
7187044 Complementary metal gate electrode technology Gang Bai 2007-03-06 $17,685,000
7067406 Thermal conducting trench in a semiconductor structure and method for forming the same Brian S. Doyle 2006-06-27 $17,073,000
7045468 Isolated junction structure and method of manufacture 2006-05-16 $12,044,000
7022559 MOSFET gate electrodes having performance tuned work functions and methods of making same John Barnak, Robert S. Chau 2006-04-04 $11,898,000
6998357 High dielectric constant metal oxide gate dielectrics Gang Bai, David B. Fraser, Brian S. Doyle, Peng Cheng 2006-02-14 $11,997,000
6879009 Integrated circuit with MOSFETS having bi-layer metal gate electrodes Jun Zheng 2005-04-12 $19,475,000
6794232 Method of making MOSFET gate electrodes with tuned work function Jun Zheng, Brian S. Doyle, Gang Bai 2004-09-21 $17,403,000
6790731 Method for tuning a work function for MOSFET gate electrodes Jun Zheng, Brian S. Doyle, Gang Bai 2004-09-14 $15,917,000
6743664 Flip-chip on flex for high performance packaging applications Larry E. Mosley, Chun Mu 2004-06-01 $40,563,000
6696333 Method of making integrated circuit with MOSFETs having bi-layer metal gate electrodes Jun Zheng 2004-02-24 $44,165,000
6689702 High dielectric constant metal oxide gate dielectrics Gang Bai, David B. Fraser, Brian S. Doyle, Peng Cheng 2004-02-10 $45,568,000
6642557 Isolated junction structure for a MOSFET 2003-11-04 $42,713,000
6624045 Thermal conducting trench in a seminconductor structure and method for forming the same Brian S. Doyle 2003-09-23 $27,638,000
6605845 Asymmetric MOSFET using spacer gate technique 2003-08-12 $56,289,000
6600364 Active interposer technology for high performance CMOS packaging application Xiao-Chun Mu 2003-07-29 $49,479,000
6528856 High dielectric constant metal oxide gate dielectrics Gang Bai, David B. Fraser, Brian S. Doyle, Peng Cheng 2003-03-04 $41,105,000
6492217 Complementary metal gates and a process for implementation Gang Bai 2002-12-10 $69,846,000
6461895 Process for making active interposer for high performance packaging applications Larry E. Mosley, Xiao-Chun Mu 2002-10-08 $34,377,000
6373111 Work function tuning for MOSFET gate electrodes Jun Zheng, Brian S. Doyle, Gang Bai 2002-04-16 $77,675,000
6365962 Flip-chip on flex for high performance packaging applications Larry E. Mosley, Xiao-Chun Mu 2002-04-02 $46,572,000
6362078 Dynamic threshold voltage device and methods for fabricating dynamic threshold voltage devices Brian S. Doyle, Brian Roberds 2002-03-26 $63,938,000
6265258 Method for making a complementary metal gate electrode technology Gang Bai 2001-07-24 $166,417,000
6222254 Thermal conducting trench in a semiconductor structure and method for forming the same Brian S. Doyle 2001-04-24 $172,753,000
6207541 Method employing silicon nitride spacers for making an integrated circuit device Siddhartha Das 2001-03-27 $117,605,000