Issued Patents All Time
Showing 351–375 of 378 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6222254 | Thermal conducting trench in a semiconductor structure and method for forming the same | Chunlin Liang | 2001-04-24 |
| 6204103 | Process to make complementary silicide metal gates for CMOS technology | Gang Bai | 2001-03-20 |
| 6197676 | Method of forming metal lines | Peng Cheng | 2001-03-06 |
| 6187694 | Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer | Peng Cheng | 2001-02-13 |
| 6162696 | Method of fabricating a feature in an integrated circuit using a two mask process with a single edge definition layer | Peng Cheng | 2000-12-19 |
| 6153342 | Selective spacer methodology for fabricating phase shift masks | Richard E. Schenker | 2000-11-28 |
| 6124185 | Method for producing a semiconductor device using delamination | — | 2000-09-26 |
| 6121093 | Method of making asymmetrical transistor structures | Peng Cheng | 2000-09-19 |
| 6103429 | Technique for fabricating phase shift masks using self-aligned spacer formation | Francisco Leon, Richard E. Schenker | 2000-08-15 |
| 6063688 | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition | Peng Cheng | 2000-05-16 |
| 6054370 | Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer | — | 2000-04-25 |
| 6025254 | Low resistance gate electrode layer and method of making same | Gang Bai | 2000-02-15 |
| 6022815 | Method of fabricating next-to-minimum-size transistor gate using mask-edge gate definition technique | Chunlin Liang, Peng Cheng, Qi-De Qian | 2000-02-08 |
| 5949108 | Semiconductor device with reduced capacitance | — | 1999-09-07 |
| 5891805 | Method of forming contacts | Peng Cheng | 1999-04-06 |
| 5891798 | Method for forming a High dielectric constant insulator in the fabrication of an integrated circuit | Jack Lee | 1999-04-06 |
| 5863832 | Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system | Quat T. Yu, Leopoldo D. Yau | 1999-01-26 |
| 5858843 | Low temperature method of forming gate electrode and gate dielectric | David B. Fraser | 1999-01-12 |
| 5834355 | Method for implanting halo structures using removable spacer | — | 1998-11-10 |
| 5717560 | ESD protection device using static capacitance coupling between drain and gate | Timothy J. Maloney | 1998-02-10 |
| 5596218 | Hot carrier-hard gate oxides by nitrogen implantation before gate oxidation | Hamid Soleimani, Ara Philipossian | 1997-01-21 |
| 5523603 | Semiconductor device with reduced time-dependent dielectric failures | Bruce J. Fishbein | 1996-06-04 |
| 5471081 | Semiconductor device with reduced time-dependent dielectric failures | Bruce J. Fishbein | 1995-11-28 |
| 5407850 | SOI transistor threshold optimization by use of gate oxide having positive charge | Ara Philipossian | 1995-04-18 |
| 5387530 | Threshold optimization for soi transistors through use of negative charge in the gate oxide | Ara Philipossian | 1995-02-07 |