Issued Patents All Time
Showing 326–350 of 378 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6656822 | Method for reduced capacitance interconnect system using gaseous implants into the ILD | Brian Roberds, Sandy Lee, Quat Vu | 2003-12-02 |
| 6653700 | Transistor structure and method of fabrication | Robert S. Chau, Jack T. Kavalieros, Anand S. Murthy, Brian Roberds | 2003-11-25 |
| 6638835 | Method for bonding and debonding films using a high-temperature polymer | Brian Roberds, Cindy Colinge | 2003-10-28 |
| 6624045 | Thermal conducting trench in a seminconductor structure and method for forming the same | Chunlin Liang | 2003-09-23 |
| 6605498 | Semiconductor transistor having a backfilled channel material | Anand S. Murthy, Brian Roberds | 2003-08-12 |
| 6596609 | Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer | Peng Cheng | 2003-07-22 |
| 6570220 | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition | Peng Cheng | 2003-05-27 |
| 6563152 | Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel | Brian Roberds | 2003-05-13 |
| 6534837 | Semiconductor device | Gang Bai | 2003-03-18 |
| 6528856 | High dielectric constant metal oxide gate dielectrics | Gang Bai, David B. Fraser, Peng Cheng, Chunlin Liang | 2003-03-04 |
| 6489655 | Integrated circuit with dynamic threshold voltage | Brian Roberds, Rafael Rios | 2002-12-03 |
| 6423614 | Method of delaminating a thin film using non-thermal techniques | — | 2002-07-23 |
| 6400015 | Method of creating shielded structures to protect semiconductor devices | David B. Fraser | 2002-06-04 |
| 6388328 | Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system | Quat Vu, Leopold Yau | 2002-05-14 |
| 6373111 | Work function tuning for MOSFET gate electrodes | Jun Zheng, Gang Bai, Chunlin Liang | 2002-04-16 |
| 6362078 | Dynamic threshold voltage device and methods for fabricating dynamic threshold voltage devices | Chunlin Liang, Brian Roberds | 2002-03-26 |
| 6362082 | Methodology for control of short channel effects in MOS transistors | Brian Roberds | 2002-03-26 |
| 6310400 | Apparatus for capacitively coupling electronic devices | Quat Vu, David B. Fraser | 2001-10-30 |
| 6306742 | Method for forming a high dielectric constant insulator in the fabrication of an integrated circuit | Jack Lee | 2001-10-23 |
| 6300221 | Method of fabricating nanoscale structures | Brian Roberds, Peng Cheng | 2001-10-09 |
| 6281532 | Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering | Brian Roberds, Jin Lee | 2001-08-28 |
| 6277765 | Low-K Dielectric layer and method of making same | Peng Cheng, Chien Chiang, Mark Thiec-Hien Tran | 2001-08-21 |
| 6261878 | Integrated circuit with dynamic threshold voltage | Brian Roberds, Rafael Rios | 2001-07-17 |
| 6238482 | Method of producing a wafer with an epitaxial quality layer and device with epitaxial quality layer | Kramadhati V. Ravi | 2001-05-29 |
| 6228694 | Method of increasing the mobility of MOS transistors by use of localized stress regions | Brian Roberds, Jin Lee | 2001-05-08 |