PS

Pat Stokley

IN Intel: 1 patents #18,218 of 30,777Top 60%
📍 Beaverton, OR: #2,113 of 3,140 inventorsTop 70%
🗺 Oregon: #17,068 of 28,073 inventorsTop 65%
Overall (All Time): #3,531,779 of 4,157,543Top 85%
1
Patents All Time

Issued Patents All Time

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6664173 Hardmask gate patterning technique for all transistors using spacer gate approach for critical dimension control Brian S. Doyle, Mark L. Doczy 2003-12-16