Issued Patents All Time
Showing 26–44 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11594533 | Stacked trigate transistors with dielectric isolation between first and second semiconductor fins | Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Aaron D. Lilak, Patrick Morrow +2 more | 2023-02-28 |
| 11573798 | Stacked transistors with different gate lengths in different device strata | Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru, Ehren Mannebach +2 more | 2023-02-07 |
| 11552104 | Stacked transistors with dielectric between channels of different device strata | Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru, Ehren Mannebach +3 more | 2023-01-10 |
| 11532719 | Transistors on heterogeneous bonding layers | Kimin Jun, Jack T. Kavalieros, Gilbert Dewey, Willy Rachmady, Aaron D. Lilak +5 more | 2022-12-20 |
| 11482621 | Vertically stacked CMOS with upfront M0 interconnect | Willy Rachmady, Patrick Morrow, Aaron D. Lilak, Rishabh Mehandru, Cheng-Ying Huang +4 more | 2022-10-25 |
| 11437405 | Transistors stacked on front-end p-type transistors | Gilbert Dewey, Patrick Morrow, Aaron D. Lilak, Willy Rachmady, Ehren Mannebach +4 more | 2022-09-06 |
| 11437283 | Backside contacts for semiconductor devices | Aaron D. Lilak, Ehren Mannebach, Richard E. Schenker, Stephanie A. Bojarski, Willy Rachmady +4 more | 2022-09-06 |
| 11430814 | Metallization structures for stacked device connectivity and their methods of fabrication | Aaron D. Lilak, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres +6 more | 2022-08-30 |
| 11424160 | Self-aligned local interconnects | Aaron D. Lilak, Ehren Mannebach, Richard E. Schenker, Stephanie A. Bojarski, Willy Rachmady +5 more | 2022-08-23 |
| 11393722 | Isolation wall stressor structures to improve channel stress and their methods of fabrication | Aaron D. Lilak, Christopher J. Jezewski, Willy Rachmady, Rishabh Mehandru, Gilbert Dewey | 2022-07-19 |
| 11393818 | Stacked transistors with Si PMOS and high mobility thin film transistor NMOS | Gilbert Dewey, Ravi Pillarisetty, Abhishek A. Sharma, Aaron D. Lilak, Willy Rachmady +5 more | 2022-07-19 |
| 11380684 | Stacked transistor architecture including nanowire or nanoribbon thin film transistors | Gilbert Dewey, Aaron D. Lilak, Cheng-Ying Huang, Jack T. Kavalieros, Willy Rachmady +4 more | 2022-07-05 |
| 11374004 | Pedestal fin structure for stacked transistor integration | Aaron D. Lilak, Rishabh Mehandru, Gilbert Dewey, Willy Rachmady, Stephen M. Cea +5 more | 2022-06-28 |
| 11374024 | Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor | Aaron D. Lilak, Rishabh Mehandru, Gilbert Dewey, Willy Rachmady | 2022-06-28 |
| 11367722 | Stacked nanowire transistor structure with different channel geometries for stress | Aaron D. Lilak, Stephen M. Cea, Gilbert Dewey, Willy Rachmady, Roza Kotlyar +4 more | 2022-06-21 |
| 11348916 | Leave-behind protective layer having secondary purpose | Aaron D. Lilak, Ehren Mannebach, Cheng-Ying Huang, Stephanie A. Bojarski, Gilbert Dewey +2 more | 2022-05-31 |
| 11342227 | Stacked transistor structures with asymmetrical terminal interconnects | Aaron D. Lilak, Ehren Mannebach, Nafees Kabir, Patrick Morrow, Gilbert Dewey +1 more | 2022-05-24 |
| 11257738 | Vertically stacked transistor devices with isolation wall structures containing an electrical conductor | Aaron D. Lilak, Patrick Morrow, Stephanie A. Bojarski | 2022-02-22 |
| 8501626 | Methods for high temperature etching a high-K material gate structure | Wei Liu, Eiichi Matsusue, Meihua Shen, Shashank Deshmukh, David Palagashvili +4 more | 2013-08-06 |