AG

Andrew F. Glew

IN Intel: 92 patents #236 of 30,777Top 1%
EL Elwha: 19 patents #66 of 232Top 30%
TI The Invention Science Fund I: 6 patents #95 of 149Top 65%
SE Searete: 1 patents #43 of 63Top 70%
MT Mips Technologies: 1 patents #18 of 35Top 55%
📍 Hillsboro, OR: #8 of 2,365 inventorsTop 1%
🗺 Oregon: #151 of 28,073 inventorsTop 1%
Overall (All Time): #9,994 of 4,157,543Top 1%
120
Patents All Time

Issued Patents All Time

Showing 76–100 of 120 patents

Patent #TitleCo-InventorsDate
5724527 Fault-tolerant boot strap mechanism for a multiprocessor system Milind Karnik, Joseph Batz, Keshavan Tiruvallur, Frank Binns, Shreekant S. Thakkar +1 more 1998-03-03
5721857 Method and apparatus for saving the effective address of floating point memory operations in an out-of-order microprocessor Jeffrey M. Abramson, Kris G. Konigsfeld, Atiq Bajwa, Warren R. Morrow, William C. Alexander 1998-02-24
5721855 Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer Glenn J. Hinton, David B. Papworth, Michael A. Fetterman, Robert P. Colwell 1998-02-24
5717882 Method and apparatus for dispatching and executing a load operation to memory Jeffrey M. Abramson, Haitham Akkary, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +2 more 1998-02-10
5708843 Method and apparatus for handling code segment violations in a computer system Jeffrey M. Abramson, Haitham Akkary, Glenn J. Hinton, Kris G. Konigsfeld, Rohit A. Vidwans 1998-01-13
5701508 Executing different instructions that cause different data type operations to be performed on single logical register file Larry M. Mennemeier, Alexander Peleg, David Bistry, Millind Mittal, Carole Dulong +4 more 1997-12-23
5694589 Instruction breakpoint detection apparatus for use in an out-of-order microprocessor Ashwani K. Gupta 1997-12-02
5694574 Method and apparatus for performing load operations in a computer system Jeffery M. Abramson, Haitham Akkary, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland 1997-12-02
5687338 Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor Darrell D. Boggs, Robert P. Colwell, Michael A. Fetterman, Ashwani K. Gupta, Glenn J. Hinton +1 more 1997-11-11
5680572 Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers Haitham Akkary, Jeffrey M. Abramson, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +2 more 1997-10-21
5671444 Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers Haitham Akkary, Jeffrey M. Abramson, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +2 more 1997-09-23
5664137 Method and apparatus for executing and dispatching store operations in a computer system Jeffrey M. Abramson, Haitham Akkary, Atig A. Bajwa, Michael A. Fetterman, Glenn J. Hinton +4 more 1997-09-02
5636374 Method and apparatus for performing operations based upon the addresses of microinstructions Scott Dion Rodgers, Keshavan Tiruvallur, Michael W. Rhodehamel, Kris G. Konigsfeld, Haitham Akkary +2 more 1997-06-03
5630075 Write combining buffer for sequentially addressed partial line operations originating from a single instruction Mandar Joshi, Nitin V. Sarangdhar 1997-05-13
5627985 Speculative and committed resource files in an out-of-order processor Michael A. Fetterman, David B. Papworth, Glenn J. Hinton, Robert P. Colwell 1997-05-06
5619664 Processor with architecture for improved pipelining of arithmetic instructions by forwarding redundant intermediate data forms 1997-04-08
5615385 Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming Michael A. Fetterman, Glenn J. Hinton, David B. Papworth, Robert P. Colwell 1997-03-25
5613132 Integer and floating point register alias table within processor device David W. Clift, James M. Arnold, Robert P. Colwell 1997-03-18
5613083 Translation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructions Haitham Akkary, Glenn J. Hinton 1997-03-18
5606670 Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system Jeffrey M. Abramson, Haitham Akkary, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +1 more 1997-02-25
5604878 Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path Robert P. Colwell, Michael A. Fetterman, Glenn J. Hinton, Robert W. Martell, David B. Papworth 1997-02-18
5590297 Address generation unit with segmented addresses in a mircroprocessor Kamla P. Huck, Scott Dion Rodgers 1996-12-31
5588126 Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system Jeffrey M. Abramson, Haitham Akkary, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +1 more 1996-12-24
5584038 Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed David B. Papworth, Michael A. Fetterman, Glenn J. Hinton, Robert P. Colwell, Steven J. Griffith +2 more 1996-12-10
5584037 Entry allocation in a circular buffer David B. Papworth, Michael A. Fetterman, Glenn J. Hinton, Robert P. Colwell, Steven J. Griffith +2 more 1996-12-10