Issued Patents All Time
Showing 51–75 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5935240 | Computer implemented method for transferring packed data between register files and memory | Larry M. Mennemeier, Alexander Peleg, Carole Dulong, Eiichi Kowashi, Millind Mittal +2 more | 1999-08-10 |
| 5913050 | Method and apparatus for providing address-size backward compatibility in a processor using segmented memory | Darrell D. Boggs, Robert P. Colwell, Michael A. Fetterman, Glenn J. Hinton, David B. Papworth | 1999-06-15 |
| 5909696 | Method and apparatus for caching system management mode information with other information | Dennis Reinhardt, James P. Kardach, John W. Horigan, Neil W. Songer | 1999-06-01 |
| 5881223 | Centralized performance monitoring architecture | Sumeet Agrawal, Patrick Franklin, Reed D. Spotten | 1999-03-09 |
| 5881262 | Method and apparatus for blocking execution of and storing load operations during their execution | Jeffery M. Abramson, Haitham Akkary, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland | 1999-03-09 |
| 5860154 | Method and apparatus for calculating effective memory addresses | Jeffrey M. Abramson, Haitham Akkary, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +1 more | 1999-01-12 |
| 5854914 | Mechanism to improved execution of misaligned loads | Milind A. Bodas, Glenn J. Hinton | 1998-12-29 |
| 5852726 | Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner | Derrick C. Lin, Romamohan R. Vakkalagadda, Larry M. Mennemeier, Alexander Peleg, David Bistry +4 more | 1998-12-22 |
| 5835748 | Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file | Doron Orenstein, Ofri Wechsler, Millind Mittal, Larry M. Mennemeier, Alexander Peleg +6 more | 1998-11-10 |
| 5826094 | Register alias table update to indicate architecturally visible state | Robert P. Colwell, David B. Papworth, Michael A. Fetterman, Glenn J. Hinton | 1998-10-20 |
| 5826109 | Method and apparatus for performing multiple load operations to the same memory location in a computer system | Jeffery M. Abramson, Haitham Akkary, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +2 more | 1998-10-20 |
| 5819079 | Instruction fetch on demand for uncacheable memory which avoids memory mapped I/O side effects in a processor with speculative instruction fetch | Ashwani K. Gupta | 1998-10-06 |
| 5809271 | Method and apparatus for changing flow of control in a processor | Robert P. Colwell, Atiq Bajwa, Michael A. Fetterman, Glenn J. Hinton, David B. Papworth | 1998-09-15 |
| 5796637 | Apparatus and method for filtering event signals | Sumeet Agrawal, Kamla P. Huck, Patrick Franklin | 1998-08-18 |
| 5778407 | Methods and apparatus for determining operating characteristics of a memory element based on its physical location | Glenn J. Hinton, David B. Papworth, Michael A. Fetterman, Robert P. Colwell, Frederick J. Pollack | 1998-07-07 |
| 5778245 | Method and apparatus for dynamic allocation of multiple buffers in a processor | David B. Papworth, Glenn J. Hinton, Robert P. Colwell, Michael A. Fetterman, Shantanu Gupta +1 more | 1998-07-07 |
| 5751983 | Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations | Jeffrey M. Abramson, David B. Papworth, Haitham Akkary, Glenn J. Hinton, Kris G. Konigsfeld +1 more | 1998-05-12 |
| 5751986 | Computer system with self-consistent ordering mechanism | Michael A. Fetterman, Glenn J. Hinton, David B. Papworth, Robert P. Colwell | 1998-05-12 |
| 5751996 | Method and apparatus for processing memory-type information within a microprocessor | Glenn J. Hinton | 1998-05-12 |
| 5749084 | Address generation unit with segmented addresses in a microprocessor | Kamla P. Huck, Scott Dion Rodgers | 1998-05-05 |
| 5748937 | Computer system that maintains processor ordering consistency by snooping an external bus for conflicts during out of order execution of memory access instructions | Jeffrey M. Abramson, Haitham Akkary, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland | 1998-05-05 |
| 5740393 | Instruction pointer limits in processor that performs speculative out-of-order instruction execution | Rohit A. Vidwans, Darrell D. Boggs, Michael A. Fetterman | 1998-04-14 |
| 5729728 | Method and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessor | Robert P. Colwell, Atiq Bajwa, Michael A. Fetterman, Glenn J. Hinton, David B. Papworth | 1998-03-17 |
| 5727176 | Data processor with circuitry for handling pointers associated with a register exchange operation | David W. Clift, James M. Arnold, Robert P. Colwell | 1998-03-10 |
| 5724536 | Method and apparatus for blocking execution of and storing load operations during their execution | Jeffery M. Abramson, Haitham Akkary, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland | 1998-03-03 |