Issued Patents All Time
Showing 101–120 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5584001 | Branch target buffer for dynamically predicting branch instruction outcomes using a predicted branch history | Bradley D. Hoyt, Glenn J. Hinton, Subramanian Natarajan | 1996-12-10 |
| 5577200 | Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system | Jeffrey M. Abramson, Haitham Akkary, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland | 1996-11-19 |
| 5574942 | Hybrid execution unit for complex microprocessor | Robert P. Colwell, David B. Papworth, Michael A. Fetterman, Glenn J. Hinton, Stephen M. Coward +1 more | 1996-11-12 |
| 5564056 | Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming | Michael A. Fetterman, Glenn J. Hinton, David B. Papworth, Robert P. Colwell | 1996-10-08 |
| 5564111 | Method and apparatus for implementing a non-blocking translation lookaside buffer | Haitham Akkary, Robert P. Colwell, Glenn J. Hinton, David B. Papworth, Michael A. Fetterman | 1996-10-08 |
| 5561814 | Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges | Glenn J. Hinton, David B. Papworth, Michael A. Fetterman, Robert P. Colwell, Frederick J. Pollack | 1996-10-01 |
| 5548776 | N-wide bypass for data dependencies within register alias table | Robert P. Colwell | 1996-08-20 |
| 5546597 | Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution | Robert W. Martell, Glenn J. Hinton, Michael A. Fetterman, David B. Papworth, Robert P. Colwell | 1996-08-13 |
| 5526510 | Method and apparatus for implementing a single clock cycle line replacement in a data cache unit | Haitham Akkary, Mandar Joshi, Rob MURRAY, Brent E. Lince, Paul D. Madland +1 more | 1996-06-11 |
| 5524262 | Apparatus and method for renaming registers in a processor and resolving data dependencies thereof | Robert P. Colwell | 1996-06-04 |
| 5517651 | Method and apparatus for loading a segment register in a microprocessor capable of operating in multiple modes | Kamla P. Huck, Scott Dion Rodgers | 1996-05-14 |
| 5499352 | Floating point register alias table FXCH and retirement floating point register array | David W. Clift, James M. Arnold, Robert P. Colwell | 1996-03-12 |
| 5497493 | High byte right-shift apparatus with a register alias table | Robert P. Colwell | 1996-03-05 |
| 5471633 | Idiom recognizer within a register alias table | Robert P. Colwell, David B. Papworth, Glenn J. Hinton, David W. Clift | 1995-11-28 |
| 5463745 | Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system | Rohit A. Vidwans, Darrell D. Boggs, Michael A. Fetterman | 1995-10-31 |
| 5452426 | Coordinating speculative and committed state register source data and immediate source data in a processor | David B. Papworth, Glenn J. Hinton, Michael A. Fetterman, Robert P. Colwell | 1995-09-19 |
| 5446912 | Partial width stalls within register alias table | Robert P. Colwell | 1995-08-29 |
| 5434987 | Method and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered store | Jeffrey M. Abramson, Haitham Akkary, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland | 1995-07-18 |
| 5420991 | Apparatus and method for maintaining processing consistency in a computer system having multiple processors | Kris G. Konigsfeld, Jeffrey M. Abramson, Haitham Akkary, Glenn J. Hinton | 1995-05-30 |
| 5404473 | Apparatus and method for handling string operations in a pipelined processor | David B. Papworth, Michael A. Fetterman, Lawrence O. Smith, Michael M. Hancock, Beth Schultz | 1995-04-04 |