Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
MK

Milind Karnik — 8 Patents

Intel: 6 patents #6,200 of 30,777Top 25%
ERElementary Robotics: 2 patents #5 of 12Top 45%
Beaverton, OR: #701 of 3,140 inventorsTop 25%
Oregon: #5,193 of 28,073 inventorsTop 20%
Overall (All Time): #600,572 of 4,157,543Top 15%
8 Patents All Time
Milind Karnik has been granted 8 US patents while listed as an inventor at Intel. The first was granted in 1996 and the most recent in July 2024. Milind Karnik ranks #600,572 of 4,157,543 US inventors in our database (top 14.4%). Patent records list Milind Karnik in Beaverton, OR, US.

Patents per Year

Patents granted per year, 1996 to 2024Bar chart with a peak of 4 patents in 1997.peak 41996: 1 patents19961997: 4 patents19971998: 1 patents19982023: 1 patents20232024: 1 patents2024

Issued Patents All Time

Showing 1–8 of 8 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12050454 Cloud-based multi-camera quality assurance lifecycle architecture Kyle Bebak, Eduardo Mancera, Arye Barnehama, Daniel Pipe-Mazo 2024-07-30
11675345 Cloud-based multi-camera quality assurance architecture Kyle Bebak, Eduardo Mancera, Arye Barnehama, Daniel Pipe-Mazo 2023-06-13
5724527 Fault-tolerant boot strap mechanism for a multiprocessor system Joseph Batz, Keshavan Tiruvallur, Andrew F. Glew, Frank Binns, Shreekant S. Thakkar +1 more 1998-03-03 $75,970,000
5687371 Selection from a plurality of bus operating speeds for a processor bus interface during processor reset Phillip G. Lee, Blair D. Milburn 1997-11-11 $176,544,000
5654988 Apparatus for generating a pulse clock signal for a multiple-stage synchronizer Deborah J. Heyward, Joseph Batz, R. Tim Frodsham 1997-08-05 $213,681,000
5636374 Method and apparatus for performing operations based upon the addresses of microinstructions Scott Dion Rodgers, Keshavan Tiruvallur, Michael W. Rhodehamel, Kris G. Konigsfeld, Andrew F. Glew +2 more 1997-06-03 $137,246,000
5619705 System and method for cascading multiple programmable interrupt controllers utilizing separate bus for broadcasting interrupt request data packet in a multi-processor system Joseph Batz 1997-04-08 $59,679,000
5524233 Method and apparatus for controlling an external cache memory wherein the cache controller is responsive to an interagent communication for performing cache control operations Blair D. Milburn, Phillip G. Lee 1996-06-04 $67,225,000