Issued Patents All Time
Showing 101–125 of 157 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6259309 | Method and apparatus for the replacement of non-operational metal lines in DRAMS | Gerhard Mueller | 2001-07-10 |
| 6246630 | Intra-unit column address increment system for memory | Kohji Hosokawa | 2001-06-12 |
| 6243306 | Defect management engine for generating a unified address to access memory cells in a primary and a redundancy memory array | — | 2001-06-05 |
| 6240043 | SDRAM with a maskable input | David R. Hanson, Gerhard Mueller | 2001-05-29 |
| 6230290 | Method of self programmed built in self test | David F. Heidel, Wei Hwang | 2001-05-08 |
| 6195300 | CBR refresh control for the redundancy array | Alexander Mitwalsky | 2001-02-27 |
| 6185712 | Chip performance optimization with self programmed built in self test | Christopher D. Wait | 2001-02-06 |
| 6185135 | Robust wordline activation delay monitor using a plurality of sample wordlines | Dmitry Netis, L. Brian Ji | 2001-02-06 |
| 6178126 | Memory and system configuration for programming a redundancy address in an electric system | Paul W. Coteus, Warren E. Maule, Steven W. Tomashot | 2001-01-23 |
| 6166981 | Method for addressing electrical fuses | Gabriel Daniel | 2000-12-26 |
| 6140855 | Dynamic-latch-receiver with self-reset pointer | Gerhard Mueller, David R. Hanson | 2000-10-31 |
| 6141267 | Defect management engine for semiconductor memories and memory systems | Louis L. Hsu, Chandrasekhar Narayan | 2000-10-31 |
| 6118726 | Shared row decoder | L. Brian Ji | 2000-09-12 |
| 6115308 | Sense amplifier and method of using the same with pipelined read, restore and write operations | David R. Hanson | 2000-09-05 |
| 6115310 | Wordline activation delay monitor using sample wordline located in data-storing array | Dmitry Netis, L. Brian Ji | 2000-09-05 |
| 6108798 | Self programmed built in self test | David F. Heidel, Wei Hwang | 2000-08-22 |
| 6081479 | Hierarchical prefetch for semiconductor memories | Brian L. Ji, Gerhard Mueller, David R. Hanson | 2000-06-27 |
| 6081021 | Conductor-insulator-conductor structure | Jeffrey P. Gambino, Chandrasekhar Narayan | 2000-06-27 |
| 6069815 | Semiconductor memory having hierarchical bit line and/or word line architecture | Gerhard Mueller, Hing Wong | 2000-05-30 |
| 6052318 | Repairable semiconductor memory circuit having parrel redundancy replacement wherein redundancy elements replace failed elements | Gabriel Daniel | 2000-04-18 |
| 6038634 | Intra-unit block addressing system for memory | L. Brian Ji | 2000-03-14 |
| 6002275 | Single ended read write drive for memory | Kohji Hosokawa | 1999-12-14 |
| 5978291 | Sub-block redundancy replacement for a giga-bit scale DRAM | — | 1999-11-02 |
| 5978931 | Variable domain redundancy replacement configuration for a memory device | Garbiel Daniel, Jean-Marc Dortu, Karl-Peter Pfefferl | 1999-11-02 |
| 5970000 | Repairable semiconductor integrated circuit memory by selective assignment of groups of redundancy elements to domains | Karl-Peter Pfefferl | 1999-10-19 |