Issued Patents All Time
Showing 126–150 of 157 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5963489 | Method and apparatus for redundancy word line replacement in a repairable semiconductor memory device | John K. DeBrosse, Yohji Watanabe, Hing Wong | 1999-10-05 |
| 5949732 | Method of structuring a multi-bank DRAM into a hierarchical column select line architecture | — | 1999-09-07 |
| 5940335 | Prioritizing the repair of faults in a semiconductor memory device | — | 1999-08-17 |
| 5917744 | Semiconductor memory having hierarchical bit line architecture with interleaved master bitlines | Gerhard Mueller | 1999-06-29 |
| 5903512 | Circuit and method to externally adjust internal circuit timing | Hing Wong, Bozidar Krsnik | 1999-05-11 |
| 5881003 | Method of making a memory device fault tolerant using a variable domain redundancy replacement configuration | Garbiel Daniel, Jean-Marc Dortu, Karl-Peter Pfefferl | 1999-03-09 |
| 5877994 | Space-efficient MDQ switch placement | Gerhard Mueller | 1999-03-02 |
| 5864496 | High density semiconductor memory having diagonal bit lines and dual word lines | Gerhard Mueller, Heinz Hoenigschmid | 1999-01-26 |
| 5848008 | Floating bitline test mode with digitally controllable bitline equalizers | Hing Wong, Bozidar Krsnik | 1998-12-08 |
| 5831912 | Semiconductor memory having space-efficient layout | Gerhard Mueller | 1998-11-03 |
| 5831913 | Method of making a memory fault-tolerant using a variable size redundancy replacement configuration | — | 1998-11-03 |
| 5831914 | Variable size redundancy replacement architecture to make a memory fault-tolerant | — | 1998-11-03 |
| 5822268 | Hierarchical column select line architecture for multi-bank DRAMs | — | 1998-10-13 |
| 5764655 | Built in self test with memory | Christopher D. Wait | 1998-06-09 |
| 5745430 | Circuit and method to externally adjust internal circuit timing | Hing Wong, Bozidar Krsnik | 1998-04-28 |
| 5745431 | Address transition detector (ATD) for power conservation | Dale E. Pontius, Steven W. Tomashot, Robert Henry Kruggel | 1998-04-28 |
| 5721485 | High performance on-chip voltage regulator designs | Louis L. Hsu, Somnuk Ratanaphanyarat, Hyun Jong Shin | 1998-02-24 |
| 5691946 | Row redundancy block architecture | John K. DeBrosse, Hing Wong | 1997-11-25 |
| 5619460 | Method of testing a random access memory | Hing Wong | 1997-04-08 |
| 5615164 | Latched row decoder for a random access memory | Hing Wong | 1997-03-25 |
| 5610867 | DRAM signal margin test method | John K. DeBrosse, Hing Wong | 1997-03-11 |
| 5561636 | Random access memory with a simple test arrangement | Yohji Watanabe | 1996-10-01 |
| 5561630 | Data sense circuit for dynamic random access memories | Daisuke Katoh, Munehiro Yoshida | 1996-10-01 |
| 5559739 | Dynamic random access memory with a simple test arrangement | John K. DeBrosse, Hing Wong | 1996-09-24 |
| 5544113 | Random access memory having a flexible array redundancy scheme | Yohji Watanabe | 1996-08-06 |