Issued Patents All Time
Showing 76–100 of 157 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6683486 | Low voltage shifter with latching function | David R. Hanson, Gerhard Mueller | 2004-01-27 |
| 6680857 | Unit-architecture with implemented limited bank-column-select repairability | Gerhard Mueller | 2004-01-20 |
| 6674676 | Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture | Louis L. Hsu, Gregory J. Fredeman, Chorng-Lii Hwang, Dale E. Pontius | 2004-01-06 |
| 6674673 | Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture | Louis L. Hsu, Gregory J. Fredeman, Chorng-Lii Hwang, Dale E. Pontius | 2004-01-06 |
| 6636978 | Rescheduling data input and output commands for bus synchronization by using digital latency shift detection | L. Brian Ji, John M. Ross | 2003-10-21 |
| 6587388 | Method and apparatus for reducing write operation time in dynamic random access memories | Sang Hoo Dhong, Hwa-Joon Oh | 2003-07-01 |
| 6552944 | Single bitline direct sensing architecture for high speed memory device | John A. Fifield, Wing K. Luk, Jeremy K. Stephens, Daniel W. Storaska | 2003-04-22 |
| 6542973 | Integrated redundancy architecture system for an embedded DRAM | Louis L. Hsu, Li-Kong Wang, Gregory J. Fredeman | 2003-04-01 |
| 6522171 | Method of reducing sub-threshold leakage in circuits during standby mode | David R. Hanson, Gerhard Mueller | 2003-02-18 |
| 6519174 | Early write DRAM architecture with vertically folded bitlines | Sang Hoo Dhong | 2003-02-11 |
| 6512683 | System and method for increasing the speed of memories | Louis L. Hsu, Li-Kong Wang | 2003-01-28 |
| 6477630 | Hierarchical row activation method for banking control in multi-bank DRAM | Brian L. Ji, Dmitry Netis | 2002-11-05 |
| 6426914 | Floating wordline using a dynamic row decoder and bitline VDD precharge | Robert H. Dennard, Louis L. Hsu | 2002-07-30 |
| 6404264 | Fuse latch having multiplexers with reduced sizes and lower power consumption | Gabriel Daniel | 2002-06-11 |
| 6404689 | Method and structure for hiding a refresh operation in a DRAM having an interlocked pipeline | Sang Hoo Dhong, Chorng-Lii Hwang | 2002-06-11 |
| 6400639 | Wordline decoder system and method | Brian L. Ji, Dmitry Netis | 2002-06-04 |
| 6370055 | Semiconductor memory having asymmetric column addressing and twisted read write drive (RWD) line architecture | David R. Hanson, Gerhard Mueller | 2002-04-09 |
| 6338103 | System for high-speed data transfer using a sequence of overlapped global pointer signals for generating corresponding sequence of non-overlapped local pointer signals | — | 2002-01-08 |
| 6335652 | Method and apparatus for the replacement of non-operational metal lines in DRAMS | Gerhard Mueller | 2002-01-01 |
| 6326800 | Self-adjusting burn-in test | — | 2001-12-04 |
| 6292402 | Prefetch write driver for a random access memory | David R. Hanson, Gerhard Mueller | 2001-09-18 |
| 6288436 | Mixed fuse technologies | Chandrasekhar Narayan, Kenneth C. Arndt, David Lachtrupp, Axel Brintzinger, Gabriel Daniel | 2001-09-11 |
| 6272062 | Semiconductor memory with programmable bitline multiplexers | Gerhard Mueller, Dmitry Netis | 2001-08-07 |
| 6266272 | Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells | Daniel W. Storaska, Chandrasekhar Narayan, William R. Tonti, Claude L. Bertin, Nick van Heel | 2001-07-24 |
| 6262615 | Dynamic logic circuit | Gerd Frankowsky | 2001-07-17 |