Issued Patents All Time
Showing 26–50 of 157 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9431339 | Wiring structure for trench fuse component with methods of fabrication | Edward P. Maciejewski, Subramanian S. Iyer, Chengwen Pei, Deepal Wehella-Gamage | 2016-08-30 |
| 9424308 | Hierarchical in-memory sort engine | Alper Buyuktosunoglu, Srivatsan Chellappa, Karthik V. Swaminathan | 2016-08-23 |
| 9418745 | Rebalancing in twin cell memory schemes to enable multiple writes | Xiang Chen, Derek H. Leu, Dan Moy | 2016-08-16 |
| 9396143 | Hierarchical in-memory sort engine | Alper Buyuktosunoglu, Srivatsan Chellappa, Karthik V. Swaminathan | 2016-07-19 |
| 9355739 | Bitline circuits for embedded charge trap multi-time-programmable-read-only-memory | Pamela Castalino, Derek H. Leu | 2016-05-31 |
| 9324430 | Method for defining a default state of a charge trap based memory cell | Sheikh Sabiq Chishti, Krishnan S. Rengarajan, Deepal Wehella-Gamage | 2016-04-26 |
| 9268863 | Hierarchical in-memory sort engine | Alper Buyuktosunoglu, Srivatsan Chellappa, Karthik V. Swaminathan | 2016-02-23 |
| 9219722 | Unclonable ID based chip-to-chip communication | Srivatsan Chellappa, Sami Rosenblatt | 2015-12-22 |
| 9208878 | Non-volatile memory based on retention modulation | Subramanian S. Iyer, Chandrasekharan Kothandaraman | 2015-12-08 |
| 9202040 | Chip authentication using multi-domain intrinsic identifiers | Sami Rosenblatt, Daniel Jacob Fainstein | 2015-12-01 |
| 9053889 | Electronic fuse cell and array | Phil C. Paone, Vimal R. Patel, Gregory J. Uhlmann | 2015-06-09 |
| 9038133 | Self-authenticating of chip based on intrinsic features | Srivatsan Chellappa, Subramanian S. Iyer, Sami Rosenblatt | 2015-05-19 |
| 9025386 | Embedded charge trap multi-time-programmable-read-only-memory for high performance logic technology | Subramanian S. Iyer, Chandrasekharan Kothandaraman, Derek H. Leu, Dan Moy | 2015-05-05 |
| 8754412 | Intra die variation monitor using through-silicon via | Xiaojun Yu, Anda C. Mocuta | 2014-06-17 |
| 8590010 | Retention based intrinsic fingerprint identification featuring a fuzzy algorithm and a dynamic key | Daniel Jacob Fainstein, Alberto Cestero, Subramanian S. Iyer, Norman W. Robson, Sami Rosenblatt | 2013-11-19 |
| 8120968 | High voltage word line driver | William Robert Reohr, John E. Barth, Jr., Derek H. Leu, Donald W. Plass | 2012-02-21 |
| 7885138 | Three dimensional twisted bitline architecture for multi-port memory | Hoki Kim | 2011-02-08 |
| 7817455 | Random access electrically programmable e-fuse ROM | Gregory J. Fredeman, Alan J. Leslie, John M. Safran | 2010-10-19 |
| 7774660 | Flexible row redundancy system | Louis L. Hsu, Gregory J. Fredeman, Rajiv V. Joshi | 2010-08-10 |
| 7764531 | Implementing precise resistance measurement for 2D array efuse bit cell using differential sense amplifier, balanced bitlines, and programmable reference resistor | Anthony Gus Aipperspach, Phil C. Paone, Brian Joy Reed, John M. Safran, David Edward Schmitt +1 more | 2010-07-27 |
| 7609577 | Design structure for improving sensing margin of electrically programmable fuses | Darren L. Anand, Gregory J. Fredeman, Alan J. Leslie, John M. Safran | 2009-10-27 |
| 7525831 | Method for improving sensing margin of electrically programmable fuses | Darren L. Anand, Gregory J. Fredeman, Alan J. Leslie, John M. Safran | 2009-04-28 |
| 7404113 | Flexible row redundancy system | Louis L. Hsu, Gregory J. Fredeman, Rajiv V. Joshi | 2008-07-22 |
| 7307911 | Apparatus and method for improving sensing margin of electrically programmable fuses | Darren L. Anand, Gregory J. Fredeman, Alan J. Leslie, John M. Safran | 2007-12-11 |
| 7286437 | Three dimensional twisted bitline architecture for multi-port memory | Hoki Kim | 2007-10-23 |