Issued Patents All Time
Showing 51–75 of 157 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7203794 | Destructive-read random access memory system buffered with destructive-read memory cache | Brian L. Ji, Chorng-Lii Hwang, Seiji Munetoh | 2007-04-10 |
| 7194670 | Command multiplier for built-in-self-test | Jonathan R. Fales, Gregory J. Fredeman, Kevin W. Gorman, Mark D. Jacunski, Alan D. Norris +2 more | 2007-03-20 |
| 7146471 | System and method for variable array architecture for memories | Gerhard Mueller, Wing K. Luk | 2006-12-05 |
| 7145829 | Single cycle refresh of multi-port dynamic random access memory (DRAM) | Hoki Kim | 2006-12-05 |
| 7093171 | Flexible row redundancy system | Louis L. Hsu, Gregory J. Fredeman, Rajiv V. Joshi | 2006-08-15 |
| 7085180 | Method and structure for enabling a redundancy allocation during a multi-bank operation | Gregory J. Fredeman, Mark D. Jacunski, Matthew R. Wordeman | 2006-08-01 |
| 7061821 | Address wrap function for addressable memory devices | Paul W. Coteus, William Paul Hovis, William Wu Shen | 2006-06-13 |
| 7057866 | System and method for disconnecting a portion of an integrated circuit | Louis L. Hsu, Rajiv V. Joshi, Chorng-Lii Hwang, Paul C. Parries | 2006-06-06 |
| 6990025 | Multi-port memory architecture | Hoki Kim, Matthew R. Wordeman | 2006-01-24 |
| 6967885 | Concurrent refresh mode with distributed row address counters in an embedded DRAM | John E. Barth, Jr., Paul C. Parries | 2005-11-22 |
| 6954387 | Dynamic random access memory with smart refresh scheduler | Hoki Kim, David R. Hanson, Gregory J. Fredeman, John W. Golz | 2005-10-11 |
| 6950353 | Cell data margin test with dummy cell | Hoki Kim | 2005-09-27 |
| 6948028 | Destructive-read random access memory system buffered with destructive-read memory cache | Brian L. Ji, Chorng-Lii Hwang, Seiji Munetoh | 2005-09-20 |
| 6947348 | Gain cell memory having read cycle interlock | Hoki Kim | 2005-09-20 |
| 6845059 | High performance gain cell architecture | Matthew R. Wordeman, John E. Barth, Jr. | 2005-01-18 |
| 6845033 | Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technology | John W. Golz | 2005-01-18 |
| 6831866 | Method and apparatus for read bitline clamping for gain cell DRAM devices | — | 2004-12-14 |
| 6829682 | Destructive read architecture for dynamic random access memories | Sang Hoo Dhong, Hwa-Joon Oh, Matthew R. Wordeman | 2004-12-07 |
| 6801980 | Destructive-read random access memory system buffered with destructive-read memory cache | Brian L. Ji, Chorng-Lii Hwang, Seiji Munetoh | 2004-10-05 |
| 6799290 | Data path calibration and testing mode using a data bus for semiconductor memories | Gerhard Mueller, David R. Hanson | 2004-09-28 |
| 6768692 | Multiple subarray DRAM having a single shared sense amplifier | Wing K. Luk | 2004-07-27 |
| 6751152 | Method and configuration to allow a lower wordline boosted voltage operation while increasing a sensing signal with access transistor threshold voltage | Louis L. Hsu, Daniel W. Storaska | 2004-06-15 |
| 6751151 | Ultra high-speed DDP-SRAM cache | Louis L. Hsu, Li-Kong Wang, Robert C. Wong | 2004-06-15 |
| 6747890 | Gain cell structure with deep trench capacitor | Subramanian S. Iyer, John W. Golz | 2004-06-08 |
| 6690198 | Repeater with reduced power consumption | Gerhard Mueller | 2004-02-10 |