DS

Daniel W. Storaska

IBM: 19 patents #5,782 of 70,183Top 9%
Overall (All Time): #240,504 of 4,157,543Top 6%
19
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8401135 Post-equalization amplitude latch-based channel characteristic measurement Troy J. Beukema, William R. Kelly, Michael A. Sorna 2013-03-19
8183949 Compensation of VCO gain curve offsets using auto-calibration Michael A. Sorna 2012-05-22
8183950 Auto-calibration for ring oscillator VCO Michael A. Sorna 2012-05-22
8040813 Apparatus and method for reduced loading of signal transmission elements Louis L. Hsu, Karl D. Selander, Michael A. Sorna 2011-10-18
8024679 Structure for apparatus for reduced loading of signal transmission elements Louis L. Hsu, Karl D. Selander, Michael A. Sorna 2011-09-20
7869544 System for measuring an eyewidth of a data signal in an asynchronous system Michael A. Sorna, William R. Kelly 2011-01-11
7352815 Data transceiver and method for equalizing the data eye of a differential input data signal Hibourahima Camara, Joseph Natonio, Karl D. Selander, Michael A. Sorna, Jeremy K. Stephens 2008-04-01
7265433 On-pad broadband matching network Edward R. Pillai, Louis L. Hsu, Wolfgang Sauter 2007-09-04
7145413 Programmable impedance matching circuit and method Louis L. Hsu, Joseph Natonio, William F. Washburn 2006-12-05
6778447 Embedded DRAM system having wide data bandwidth and data transfer data protocol Louis L. Hsu, Rajiv V. Joshi, Jeremy K. Stephens 2004-08-17
6775736 Embedded DRAM system having wide data bandwidth and data transfer data protocol Louis L. Hsu, Rajiv J. Joshi, Jeremy K. Stephens 2004-08-10
6751152 Method and configuration to allow a lower wordline boosted voltage operation while increasing a sensing signal with access transistor threshold voltage Louis L. Hsu, Toshiaki Kirihata 2004-06-15
6711078 Writeback and refresh circuitry for direct sensed DRAM macro Ciaran J. Brennan, John A. Fifield, Jeremy K. Stephens 2004-03-23
6614714 Semiconductor memory system having a data clock system for reliable high-speed data transfers Louis L. Hsu, Jeremy K. Stephens, Li-Kong Wang 2003-09-02
6552944 Single bitline direct sensing architecture for high speed memory device John A. Fifield, Toshiaki Kirihata, Wing K. Luk, Jeremy K. Stephens 2003-04-22
6449202 DRAM direct sensing scheme Hiroyuki Akatsu, Louis L. Hsu, Jeremy K. Stephens 2002-09-10
6445611 Method and arrangement for preconditioning in a destructive read memory John A. Fifield, Chorng-Lii Hwang 2002-09-03
6438051 Stabilized direct sensing memory architecture John A. Fifield, Wing K. Luk 2002-08-20
6266272 Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells Toshiaki Kirihata, Chandrasekhar Narayan, William R. Tonti, Claude L. Bertin, Nick van Heel 2001-07-24