Issued Patents All Time
Showing 51–75 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7687829 | Stressed field effect transistors on hybrid orientation substrate | Dureseti Chidambarrao, Judson R. Holt, Meikei Ieong, Siddhartha Panda | 2010-03-30 |
| 7679121 | Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof | Jack O. Chu | 2010-03-16 |
| 7678634 | Local stress engineering for CMOS devices | Kathryn T. Schonenberg | 2010-03-16 |
| 7619300 | Super hybrid SOI CMOS devices | Meikei Ieong | 2009-11-17 |
| 7618857 | Method of reducing detrimental STI-induced stress in MOSFET channels | Meikei Leong, Chun-Yung Sung | 2009-11-17 |
| 7598147 | Method of forming CMOS with Si:C source/drain by laser melting and recrystallization | Yaocheng Liu, Kathryn T. Schonenberg, Chun-Yung Sung | 2009-10-06 |
| 7569442 | High speed lateral heterojunction MISFETS realized by 2-dimensional bandgap engineering and methods thereof | Jack O. Chu | 2009-08-04 |
| 7547641 | Super hybrid SOI CMOS devices | Meikei Ieong | 2009-06-16 |
| 7528050 | High performance field effect transistors on SOI substrate with stress-inducing material as buried insulator and methods | Judson R. Holt | 2009-05-05 |
| 7525161 | Strained MOS devices using source/drain epitaxy | Meikei Ieong, Xiao Hu Liu, Siddhartha Panda, Haizhou Yin | 2009-04-28 |
| 7510904 | Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector | Jack O. Chu, Gabriel Dehlinger, Alfred Grill, Steven J. Koester, Jeremy D. Schaub | 2009-03-31 |
| 7485537 | Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness | Herbert L. Ho, Mahender Kumar, Paul A. Papworth, Christopher D. Sheraw, Michael D. Steigerwalt | 2009-02-03 |
| 7453113 | Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof | Jack O. Chu | 2008-11-18 |
| 7393735 | Structure for and method of fabricating a high-mobility field-effect transistor | Jack O. Chu, Steven J. Koester | 2008-07-01 |
| 7381655 | Mandrel/trim alignment in SIT processing | Toshiharu Furukawa, David V. Horak, Charles W. Koburger, III | 2008-06-03 |
| 7375410 | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof | Herbert L. Ho, Mahender Kumar, Paul A. Papworth, Christopher D. Sheraw, Michael D. Steigerwalt | 2008-05-20 |
| 7368358 | Method for producing field effect device that includes epitaxially growing SiGe source/drain regions laterally from a silicon body | Xiangdong Chen | 2008-05-06 |
| 7354822 | Method of forming a MOSFET with dual work function materials | Xiangdong Chen, Geng Wang, Yujun Li | 2008-04-08 |
| 7348611 | Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereof | Meikei Ieong, Kern Rim | 2008-03-25 |
| 7342294 | SOI bipolar transistors with reduced self heating | Kai Xiu | 2008-03-11 |
| 7309626 | Quasi self-aligned source/drain FinFET process | Mei-Kei Ieong, Thomas Ludwig, Edward J. Nowak | 2007-12-18 |
| 7294879 | Vertical MOSFET with dual work function materials | Xiangdong Chen, Geng Wang, Yujun Li | 2007-11-13 |
| 7227205 | Strained-silicon CMOS device and method | Andres Bryant, Kern Rim | 2007-06-05 |
| 7205604 | Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof | Jack O. Chu | 2007-04-17 |
| 7161220 | High speed photodiode with a barrier layer for blocking or eliminating slow photonic carriers and method for forming same | Guy M. Cohen, Jeremy D. Schaub | 2007-01-09 |