Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8963294 | Dense chevron finFET and method of manufacturing same | Jochen Beintner, Edward J. Nowak | 2015-02-24 |
| 8762919 | Circuit macro placement using macro aspect ratio based on ports | Joachim Keinert, Juergen Koehl | 2014-06-24 |
| 8495551 | Shaping ports in integrated circuit design | Joachim Keinert | 2013-07-23 |
| 8429584 | Method, electronic design automation tool, computer program product, and data processing program for creating a layout for design representation of an electronic circuit and corresponding port for an electronic circuit | Joachim Keinert | 2013-04-23 |
| 8423947 | Gridded glyph geometric objects (L3GO) design method | Mark A. Lavin, Gregory A. Northrop, Robert T. Sayah | 2013-04-16 |
| 8418110 | Using port obscurity factors to improve routing | Joachim Keinert | 2013-04-09 |
| 8020120 | Layout quality gauge for integrated circuit design | Fook-Luen Heng, Mark A. Lavin, Jin-Fuw Lee, Rama Nand Sing, Fanchieh Yee | 2011-09-13 |
| 7990158 | Measurement arrangement for determining the characteristic line parameters by measuring scattering parameters | Helmut Schettler, Thomas-Michael Winkel | 2011-08-02 |
| 7962877 | Port assignment in hierarchical designs by abstracting macro logic | Joachim Keinert, Juergen Koehl | 2011-06-14 |
| 7851283 | Field effect transistor with raised source/drain fin straps | Brent A. Anderson, Edward J. Nowak | 2010-12-14 |
| 7456471 | Field effect transistor with raised source/drain fin straps | Brent A. Anderson, Edward J. Nowak | 2008-11-25 |
| 7323374 | Dense chevron finFET and method of manufacturing same | Jochen Beintner, Edward J. Nowak | 2008-01-29 |
| 7315994 | Method and device for automated layer generation for double-gate FinFET designs | Ingo Aller, Veit Gernhoefer, Joachim Keinert | 2008-01-01 |
| 7309626 | Quasi self-aligned source/drain FinFET process | Mei-Kei Ieong, Edward J. Nowak, Qiqing C. Ouyang | 2007-12-18 |
| 6909147 | Multi-height FinFETS | Ingo Aller, Joachim Keinert, Edward J. Nowak, BethAnn Rainey | 2005-06-21 |
| 5944772 | Combined adder and logic unit | Juergen Haas, Wilhelm Haller, Ulrich Krauch, Holger Wetter | 1999-08-31 |
| 5928319 | Combined binary/decimal adder unit | Wilhelm Haller, Ulrich Krauch, Holger Wetter | 1999-07-27 |
| 5744996 | CMOS integrated semiconductor circuit | Gunther Kotzle, Volker Kreuter, Helmut Schettler | 1998-04-28 |
| 5680063 | Bi-directional voltage translator | Richard Ng | 1997-10-21 |
| 5306866 | Module for electronic package | Harald Gruber, Heinz G. Horbach, Gunther Kotzle, Helmut Schettler | 1994-04-26 |
| 5162264 | Integrated circuit package | Werner Haug, Erich Klink, Karl E. Kroll, Helmut Schettler, Rainer Stahl +1 more | 1992-11-10 |
| 5016087 | Integrated circuit package | Werner Haug, Erich Klink, Karl E. Kroll, Helmut Schettler, Rainer Stahl +1 more | 1991-05-14 |
| 4967104 | Circuit for increasing the output impedance of an amplifier | Helmut Schettler, Otto Wagner, Rainer Zuhlke | 1990-10-30 |
| 4815113 | Method for digital slope control of output signals of power amplifiers in semiconductor chips | Helmut Schettler, Otto Wagner, Rainer Zuhlke | 1989-03-21 |