Issued Patents All Time
Showing 26–50 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9443963 | SiGe FinFET with improved junction doping control | Pranita Kerber, Alexander Reznicek | 2016-09-13 |
| 9443873 | Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step | Pranita Kerber, Alexander Reznicek, Dominic J. Schepis | 2016-09-13 |
| 9412865 | Reduced resistance short-channel InGaAs planar MOSFET | Pranita Kerber, Alexander Reznicek | 2016-08-09 |
| 9391173 | FinFET device with vertical silicide on recessed source/drain epitaxy regions | Keith E. Fogel, Pranita Kerber, Alexander Reznicek | 2016-07-12 |
| 9391198 | Strained semiconductor trampoline | Pranita Kerber, Alexander Reznicek, Dominic J. Schepis | 2016-07-12 |
| 9379219 | SiGe finFET with improved junction doping control | Pranita Kerber, Alexander Reznicek | 2016-06-28 |
| 9276118 | FinFET device having a merge source drain region under contact areas and unmerged fins between contact areas, and a method of manufacturing same | Pranita Kerber, Alexander Reznicek | 2016-03-01 |
| 9275908 | Semiconductor device including gate channel having adjusted threshold voltage | Pranita Kerber, Alexander Reznicek | 2016-03-01 |
| 9230992 | Semiconductor device including gate channel having adjusted threshold voltage | Pranita Kerber, Alexander Reznicek | 2016-01-05 |
| 8993406 | FinFET device having a merged source drain region under contact areas and unmerged fins between contact areas, and a method of manufacturing same | Pranita Kerber, Alexander Reznicek | 2015-03-31 |
| 8895395 | Reduced resistance SiGe FinFET devices and method of forming same | Pranita Kerber, Alexander Reznicek | 2014-11-25 |
| 8664721 | FET with FUSI gate and reduced source/drain contact resistance | Christian Lavoie, Tak H. Ning, Paul M. Solomon, Zhen Zhang | 2014-03-04 |
| 8587063 | Hybrid double box back gate silicon-on-insulator wafers with enhanced mobility channels | Robert H. Dennard, Jeng-Bang Yau | 2013-11-19 |
| 8063424 | Embedded photodetector apparatus in a 3D CMOS chip stack | Fadi H. Gebara, Tak H. Ning, Jeremy D. Schaub | 2011-11-22 |
| 7968915 | Dual stress memorization technique for CMOS application | Thomas S. Kanarsky, Haizhou Yin | 2011-06-28 |
| 7968946 | Higher performance CMOS on (110) wafers | Massimo V. Fischetti | 2011-06-28 |
| 7915653 | Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector | Jack O. Chu, Gabriel Dehlinger, Alfred Grill, Steven J. Koester, Jeremy D. Schaub | 2011-03-29 |
| 7911024 | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof | Herbert L. Ho, Mahender Kumar, Paul A. Papworth, Christopher D. Sheraw, Michael D. Steigerwalt | 2011-03-22 |
| 7902012 | High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof | Jack O. Chu | 2011-03-08 |
| 7872303 | FinFET with longitudinal stress in a channel | Kevin K. Chan, Dae-Gyu Park, Xinhui Wang | 2011-01-18 |
| 7863197 | Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification | Huajie Chen, Dureseti Chidambarrao, Judson R. Holt, Siddhartha Panda | 2011-01-04 |
| 7834399 | Dual stress memorization technique for CMOS application | Thomas S. Kanarsky, Haizhou Yin | 2010-11-16 |
| 7808081 | Strained-silicon CMOS device and method | Andres Bryant, Kern Rim | 2010-10-05 |
| 7763518 | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof | Herbert L. Ho, Mahender Kumar, Paul A. Papworth, Christopher D. Sheraw, Michael D. Steigerwalt | 2010-07-27 |
| 7705345 | High performance strained silicon FinFETs device and method for forming same | Stephen W. Bedell, Kevin K. Chan, Dureseti Chidambarrao, Silke H. Christianson, Jack O. Chu +4 more | 2010-04-27 |