| 11869783 |
Optimizating semiconductor binning by feed-forward process adjustment |
Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Theodorus E. Standaert, James H. Stathis |
2024-01-09 |
| 11869808 |
Top via process with damascene metal |
Lawrence A. Clevenger, Brent A. Anderson, Christopher J. Penny, Kisik Choi, Robert R. Robison |
2024-01-09 |
| 11854884 |
Fully aligned top vias |
Koichi Motoyama, Somnath Ghosh, Christopher J. Penny, Robert R. Robison, Lawrence A. Clevenger |
2023-12-26 |
| 11842961 |
Advanced metal interconnects with a replacement metal |
Lawrence A. Clevenger, Kisik Choi, Brent A. Anderson |
2023-12-12 |
| 11823998 |
Top via with next level line selective growth |
Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Robert R. Robison |
2023-11-21 |
| 11804406 |
Top via cut fill process for line extension reduction |
Christopher J. Penny, Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Robert R. Robison |
2023-10-31 |
| 11791258 |
Conductive lines with subtractive cuts |
Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Christopher J. Penny, Robert R. Robison |
2023-10-17 |
| 11756887 |
Backside floating metal for increased capacitance |
Hosadurga Shobha, Huai Huang, Lawrence A. Clevenger |
2023-09-12 |
| 11749602 |
Topological semi-metal interconnects |
Ching-Tzu Chen, Vijay Narayanan, Takeshi Nogami |
2023-09-05 |
| 11735475 |
Removal of barrier and liner layers from a bottom of a via |
Chanro Park, Koichi Motoyama, Kenneth Chun Kuen Cheng |
2023-08-22 |
| 11682617 |
High aspect ratio vias for integrated circuits |
Somnath Ghosh, Lawrence A. Clevenger, Robert R. Robison |
2023-06-20 |
| 11670542 |
Stepped top via for via resistance reduction |
Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Robert R. Robison |
2023-06-06 |
| 11621189 |
Barrier-less prefilled via formation |
Hosadurga Shobha, Junli Wang, Lawrence A. Clevenger, Christopher J. Penny, Robert R. Robison +1 more |
2023-04-04 |
| 11600565 |
Top via stack |
Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Robert R. Robison |
2023-03-07 |
| 11488863 |
Self-aligned contact scheme for pillar-based memory elements |
Benjamin D. Briggs, Michael Rizzolo |
2022-11-01 |
| 11444029 |
Back-end-of-line interconnect structures with varying aspect ratios |
Prasad Bhosale, Michael Rizzolo, Chih-Chao Yang |
2022-09-13 |
| 11437317 |
Single-mask alternating line deposition |
Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Robert R. Robison |
2022-09-06 |
| 11430735 |
Barrier removal for conductor in top via integration scheme |
Brent A. Anderson, Christopher J. Penny, Lawrence A. Clevenger, Kisik Choi, Robert R. Robison |
2022-08-30 |
| 11348872 |
Hybrid dielectric scheme for varying liner thickness and manganese concentration |
Benjamin D. Briggs, Lawrence A. Clevenger, Takeshi Nogami, Christopher J. Penny, Michael Rizzolo |
2022-05-31 |
| 11315827 |
Skip via connection between metallization levels |
Huai Huang, Lawrence A. Clevenger, Hosadurga Shobha, Christopher J. Penny |
2022-04-26 |
| 11302575 |
Subtractive line with damascene second line type |
Brent A. Anderson, Christopher J. Penny, Lawrence A. Clevenger, Kisik Choi, Robert R. Robison |
2022-04-12 |
| 11295978 |
Interconnects having spacers for improved top via critical dimension and overlay tolerance |
Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Robert R. Robison |
2022-04-05 |
| 11289371 |
Top vias with selectively retained etch stops |
Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Robert R. Robison |
2022-03-29 |
| 11276611 |
Top via on subtractively etched conductive line |
Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Christopher J. Penny, Robert R. Robison |
2022-03-15 |
| 11276639 |
Conductive lines with subtractive cuts |
Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Christopher J. Penny, Robert R. Robison |
2022-03-15 |
