KT

Krishna R. Tunga

IBM: 41 patents #2,268 of 70,183Top 4%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
ET Elpis Technologies: 1 patents #31 of 121Top 30%
📍 Wappingers Falls, NY: #41 of 884 inventorsTop 5%
🗺 New York: #2,285 of 115,490 inventorsTop 2%
Overall (All Time): #67,594 of 4,157,543Top 2%
44
Patents All Time

Issued Patents All Time

Showing 26–44 of 44 patents

Patent #TitleCo-InventorsDate
10424527 Electronic package with tapered pedestal Kamal K. Sikka, Hilton T. Toy, Thomas Weiss 2019-09-24
10381276 Test cell for laminate and method Sushumna Iruvanti, Shidong Li, Marek A. Orlowski, David L. Questad, Tuhin Sinha +3 more 2019-08-13
10373925 Metal pad modification Ekta Misra 2019-08-06
10325830 Multipart lid for a semiconductor package with multiple components Charles L. Arvin, Steven P. Ostrander 2019-06-18
10276534 Reduction of solder interconnect stress Anson J. Call, Vijayeshwar D. Khanna, David J. Russell 2019-04-30
10276535 Method of fabricating contacts of an electronic package structure to reduce solder interconnect stress Anson J. Call, Vijayeshwar D. Khanna, David J. Russell 2019-04-30
10249548 Test cell for laminate and method Sushumna Iruvanti, Shidong Li, Marek A. Orlowski, David L. Questad, Tuhin Sinha +3 more 2019-04-02
10108753 Laminate substrate thermal warpage prediction for designing a laminate substrate Anson J. Call, Vijayeshwar D. Khanna, David J. Russell 2018-10-23
10096557 Tiled-stress-alleviating pad structure Ekta Misra, Mukta G. Farooq 2018-10-09
10090271 Metal pad modification Ekta Misra 2018-10-02
9947598 Determining crackstop strength of integrated circuit assembly at the wafer level Karen P. McLaughlin, Charles L. Arvin, Brian R. Sundlof, Steven P. Ostrander, Christopher D. Muzzy +1 more 2018-04-17
9865557 Reduction of solder interconnect stress Anson J. Call, Vijayeshwar D. Khanna, David J. Russell 2018-01-09
9842810 Tiled-stress-alleviating pad structure Ekta Misra, Mukta G. Farooq 2017-12-12
9837333 Electronic package cover having underside rib Kamal K. Sikka 2017-12-05
9754905 Final passivation for wafer level warpage and ULK stress reduction Ekta Misra 2017-09-05
9563732 In-plane copper imbalance for warpage prediction Anson J. Call, Vijayeshwar D. Khanna, David J. Russell 2017-02-07
9105500 Non-hermetic sealed multi-chip module package Paul F. Bodenweber, Hilton T. Toy, Jeffrey A. Zitz 2015-08-11
8860206 Multichip electronic packages and methods of manufacture Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz 2014-10-14
8592970 Multichip electronic packages and methods of manufacture Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz 2013-11-26