JS

Julien Sylvestre

IBM: 18 patents #6,125 of 70,183Top 9%
📍 Chambly, CA: #2 of 72 inventorsTop 3%
Overall (All Time): #238,708 of 4,157,543Top 6%
19
Patents All Time

Issued Patents All Time

Showing 1–19 of 19 patents

Patent #TitleCo-InventorsDate
10390460 Apparatus and methods for cooling of an integrated circuit Simon Jasmin 2019-08-20
10134704 Thermocompression for semiconductor chip assembly 2018-11-20
9761542 Liquid metal flip chip devices ASSANE NDIEGUENE, Pierre Albert 2017-09-12
9735125 Thermocompression for semiconductor chip assembly 2017-08-15
9698072 Low-stress dual underfill packaging Peter J. Brofman, Marie-Claude Paquet 2017-07-04
9373559 Low-stress dual underfill packaging Peter J. Brofman, Marie-Claude Paquet 2016-06-21
9287230 Thermocompression for semiconductor chip assembly 2016-03-15
8939346 Methods and systems involving soldering 2015-01-27
8932909 Thermocompression for semiconductor chip assembly 2015-01-13
8910853 Additives for grain fragmentation in Pb-free Sn-based solder Charles L. Arvin, Alexandre Blander, Peter J. Brofman, Donald W. Henderson, Gareth G. Hougham +7 more 2014-12-16
8796049 Underfill adhesion measurements at a microscopic scale Maxime Cadotte, Marie-Claude Paquet 2014-08-05
8493746 Additives for grain fragmentation in Pb-free Sn-based solder Charles L. Arvin, Alexandre Blander, Peter J. Brofman, Donald W. Henderson, Gareth G. Hougham +7 more 2013-07-23
8197612 Optimization of metallurgical properties of a solder joint James A. Busby, Minhua Lu, Valerie Oberson, Eric D. Perfecto, Kamalesh K. Srivastava +2 more 2012-06-12
7538432 Temporary structure to reduce stress and warpage in a flip chip organic package David Danovitch 2009-05-26
7512518 Method for measuring thin layers in solid state devices Alexandre Blander, Richard Brassard, Carl Savard 2009-03-31
7498198 Structure and method for stress reduction in flip chip microelectronic packages using underfill materials with spatially varying properties Sylvie Charles, David Danovitch, Sylvain Ouimet 2009-03-03
7482180 Method for determining the impact of layer thicknesses on laminate warpage Jean Audet, Marco Gauvin, Sylvain Pharand 2009-01-27
7484190 Method to optimize the manufacturing of interconnects in microelectronic packages Eric Duchesne 2009-01-27
7473618 Temporary structure to reduce stress and warpage in a flip chip organic package David Danovitch 2009-01-06