Issued Patents All Time
Showing 76–97 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9893166 | Dummy gate formation using spacer pull down hardmask | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Sean Teehan | 2018-02-13 |
| 9882048 | Gate cut on a vertical field effect transistor with a defined-width inorganic mask | Brent A. Anderson, Sivananda K. Kanakasabapathy, Jeffrey C. Shearer, Stuart A. Sieg, Junli Wang | 2018-01-30 |
| 9842739 | Method and structure for enabling high aspect ratio sacrificial gates | Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Jeffrey C. Shearer, Sean Teehan | 2017-12-12 |
| 9786666 | Method to form dual channel semiconductor material fins | Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Eric R. Miller, Sean Teehan | 2017-10-10 |
| 9768075 | Method and structure to enable dual channel fin critical dimension control | Marc A. Bergendahl, Kangguo Cheng, Sean Teehan | 2017-09-19 |
| 9754942 | Single spacer for complementary metal oxide semiconductor process flow | Marc A. Bergendahl, Kangguo Cheng, Jessica Dechene, Fee Li Lie, Eric R. Miller +2 more | 2017-09-05 |
| 9748146 | Single spacer for complementary metal oxide semiconductor process flow | Marc A. Bergendahl, Kangguo Cheng, Jessica Dechene, Fee Li Lie, Eric R. Miller +2 more | 2017-08-29 |
| 9741856 | Stress retention in fins of fin field-effect transistors | Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Fee Li Lie, Stuart A. Sieg | 2017-08-22 |
| 9741823 | Fin cut during replacement gate formation | Andrew M. Greene, Balasubramanian Pranatharthiharan, Sivananda K. Kanakasabapathy | 2017-08-22 |
| 9728622 | Dummy gate formation using spacer pull down hardmask | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Sean Teehan | 2017-08-08 |
| 9721848 | Cutting fins and gates in CMOS devices | Huiming Bu, Kangguo Cheng, Andrew M. Greene, Dechao Guo, Sivananda K. Kanakasabapathy +6 more | 2017-08-01 |
| 9716184 | Enabling large feature alignment marks with sidewall image transfer patterning | Kangguo Cheng, Sivananda K. Kanakasabapathy, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer +1 more | 2017-07-25 |
| 9673199 | Gate cutting for a vertical transistor device | Brent A. Anderson, Sivananda K. Kanakasabapathy, Stuart A. Sieg, Junli Wang | 2017-06-06 |
| 9659779 | Method and structure for enabling high aspect ratio sacrificial gates | Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Jeffrey C. Shearer, Sean Teehan | 2017-05-23 |
| 9627277 | Method and structure for enabling controlled spacer RIE | Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer +1 more | 2017-04-18 |
| 9620590 | Nanosheet channel-to-source and drain isolation | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Sean Teehan | 2017-04-11 |
| 9608065 | Air gap spacer for metal gates | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Sean Teehan | 2017-03-28 |
| 9536744 | Enabling large feature alignment marks with sidewall image transfer patterning | Kangguo Cheng, Sivananda K. Kanakasabapathy, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer +1 more | 2017-01-03 |
| 9450095 | Single spacer for complementary metal oxide semiconductor process flow | Marc A. Bergendahl, Kangguo Cheng, Jessica Dechene, Fee Li Lie, Eric R. Miller +2 more | 2016-09-20 |
| 9362179 | Method to form dual channel semiconductor material fins | Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Eric R. Miller, Sean Teehan | 2016-06-07 |
| 9318574 | Method and structure for enabling high aspect ratio sacrificial gates | Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Jeffrey C. Shearer, Sean Teehan | 2016-04-19 |
| 9171733 | Method of selectively etching a three-dimensional structure | David N. Ruzic | 2015-10-27 |