Issued Patents All Time
Showing 76–100 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7549098 | Redundancy programming for a memory device | Kevin W. Gorman | 2009-06-16 |
| 7489582 | Low overhead switched header power savings apparatus | Harold Pilo, Vinod Ramadurai | 2009-02-10 |
| 7400546 | Low overhead switched header power savings apparatus | Harold Pilo, Vinod Ramadurai | 2008-07-15 |
| 7382672 | Differential and hierarchical sensing for memory circuits | Paul C. Parries, William Robert Reohr, Matthew R. Wordeman | 2008-06-03 |
| 7342839 | Memory cell access circuit | — | 2008-03-11 |
| 7286425 | System and method for capacitive mis-match bit-line sensing | — | 2007-10-23 |
| 7286385 | Differential and hierarchical sensing for memory circuits | Paul C. Parries, William Robert Reohr, Matthew R. Wordeman | 2007-10-23 |
| 7243279 | Method for separating shift and scan paths on scan-only, single port LSSD latches | Darren L. Anand, Steven F. Oakland, Michael R. Ouellette | 2007-07-10 |
| 7193262 | Low-cost deep trench decoupling capacitor device and process of manufacture | Herbert L. Ho, Ramachandra Divakaruni, Wayne F. Ellis, Johnathan E. Faltermeier, Brent A. Anderson +4 more | 2007-03-20 |
| 7089136 | Method for reduced electrical fusing time | Darren L. Anand, Steven F. Oakland, Michael R. Ouellette | 2006-08-08 |
| 7085971 | ECC based system and method for repairing failed memory elements | Wayne F. Ellis, John A. Fifield | 2006-08-01 |
| 7061793 | Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices | George M. Braceras, Harold Pilo | 2006-06-13 |
| 7046565 | Bi-mode sense amplifier with dual utilization of the reference cells and dual precharge scheme for improving data retention | Hoki Kim | 2006-05-16 |
| 7012826 | Bitline twisting structure for memory arrays incorporating reference wordlines | — | 2006-03-14 |
| 6995585 | System and method for implementing self-timed decoded data paths in integrated circuits | Darren L. Anand | 2006-02-07 |
| 6967885 | Concurrent refresh mode with distributed row address counters in an embedded DRAM | Toshiaki Kirihata, Paul C. Parries | 2005-11-22 |
| 6957372 | Repair of address-specific leakage | Paul C. Parries, Norman W. Robson | 2005-10-18 |
| 6845059 | High performance gain cell architecture | Matthew R. Wordeman, Toshiaki Kirihata | 2005-01-18 |
| 6791348 | Digital overcurrent test | Paul C. Parries | 2004-09-14 |
| 6788591 | System and method for direct write to dynamic random access memory (DRAM) using PFET bit-switch | Darren L. Anand | 2004-09-07 |
| 6766468 | Memory BIST and repair | Jeffrey H. Dreibelbis, Michael R. Ouellette | 2004-07-20 |
| 6738300 | Direct read of DRAM cell using high transfer ratio | — | 2004-05-18 |
| 6728159 | Flexible multibanking interface for embedded memory applications | Darren L. Anand | 2004-04-27 |
| 6577156 | Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox | Darren L. Anand, John A. Fifield, Pamela S. Gillis, Peter O. Jakobsen, Douglas W. Kemerer +4 more | 2003-06-10 |
| 6577548 | Self timing interlock circuit for embedded DRAM | Jeffrey H. Dreibelbis, Erik A. Nelson | 2003-06-10 |