JJ

John E. Barth, Jr.

IBM: 100 patents #566 of 70,183Top 1%
SY Synopsys: 7 patents #152 of 2,302Top 7%
Globalfoundries: 4 patents #817 of 4,424Top 20%
IN Invecas: 4 patents #3 of 22Top 15%
Infineon Technologies Ag: 1 patents #4,439 of 7,486Top 60%
📍 Williston, VT: #3 of 203 inventorsTop 2%
🗺 Vermont: #42 of 4,968 inventorsTop 1%
Overall (All Time): #10,850 of 4,157,543Top 1%
115
Patents All Time

Issued Patents All Time

Showing 101–115 of 115 patents

Patent #TitleCo-InventorsDate
6552938 Column redundancy system and method for embedded DRAM devices with multibanking capability Darren L. Anand 2003-04-22
6507511 Secure and dense SRAM cells in EDRAM technology Subramanian S. Iyer, Babar A. Khan, Robert C. Wong 2003-01-14
6504766 System and method for early write to memory by injecting small voltage signal Harold Pilo 2003-01-07
6426904 Structures for wafer level test and burn-in Claude L. Bertin, Jeffrey H. Dreibelbis, Wayne F. Ellis, Wayne J. Howell, Erik L. Hedberg +3 more 2002-07-30
6400629 System and method for early write to memory by holding bitline at fixed potential Harold Pilo 2002-06-04
6272054 Twin-cell memory architecture with shielded bitlines for embedded memory applications John A. Fifield 2001-08-07
6233184 Structures for wafer level test and burn-in Claude L. Bertin, Jeffrey H. Dreibelbis, Wayne F. Ellis, Wayne J. Howell, Erik L. Hedberg +3 more 2001-05-15
6044024 Interactive method for self-adjusted access on embedded DRAM memory macros Jeffrey H. Dreibelbis, Howard L. Kalter 2000-03-28
5961653 Processor based BIST for an embedded memory Howard L. Kalter, Jeffrey H. Dreibelbis, Rex Kho, John Stuart Parenteau, Jr., Donald L. Wheater +1 more 1999-10-05
5796662 Integrated circuit chip with a wide I/O memory array and redundant data lines Howard L. Kalter 1998-08-18
5740068 Fidelity enhancement of lithographic and reactive-ion-etched images by optical proximity correction Lars Liebmann, Robert T. Sayah 1998-04-14
5663924 Boundary independent bit decode for a SDRAM Howard L. Kalter 1997-09-02
5241500 Method for setting test voltages in a flash write mode Howard L. Kalter 1993-08-31
5134616 Dynamic RAM with on-chip ECC and optimized bit and word redundancy Charles E. Drake, John A. Fifield, William Paul Hovis, Howard L. Kalter, Scott C. Lewis +3 more 1992-07-28
4999815 Low power addressing systems Charles E. Drake, William Paul Hovis, Howard L. Kalter, Gordon A. Kelley, Jr., Scott C. Lewis +2 more 1991-03-12