Issued Patents All Time
Showing 176–200 of 289 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8575009 | Two-step hydrogen annealing process for creating uniform non-planar semiconductor devices at aggressive pitch | Sarunya Bangsaruntip | 2013-11-05 |
| 8564025 | Nanowire FET having induced radial strain | Sarunya Bangsaruntip, Guy M. Cohen, Conal E. Murray | 2013-10-22 |
| 8563376 | Hybrid CMOS nanowire mesh device and bulk CMOS device | Josephine B. Chang, Leland Chang, Chung-Hsun Lin | 2013-10-22 |
| 8558219 | Nanowire field effect transistors | Sarunya Bangsaruntip, Guy M. Cohen, Amlan Majumdar | 2013-10-15 |
| 8557648 | Recessed source and drain regions for FinFETs | Josephine B. Chang, Paul Chang, Michael A. Guillorn, Chung-Hsun Lin | 2013-10-15 |
| 8551833 | Double gate planar field effect transistors | Josephine B. Chang, Leland Chang, Chung-Hsun Lin | 2013-10-08 |
| 8546920 | Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) | Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar Singh | 2013-10-01 |
| 8546269 | Top-down nanowire thinning processes | Tymon Barwicz, Guy M. Cohen, Lidija Sekaric | 2013-10-01 |
| 8541295 | Pad-less gate-all around semiconductor nanowire FETs on bulk semiconductor wafers | Josephine B. Chang, Isaac Laurer, Shreesh Narasimha | 2013-09-24 |
| 8541774 | Hybrid CMOS technology with nanowire devices and double gated planar devices | Sarunya Bangsaruntip, Josephine B. Chang, Leland Chang | 2013-09-24 |
| 8536029 | Nanowire FET and finFET | Josephine B. Chang, Chung-Hsun Lin | 2013-09-17 |
| 8536041 | Method for fabricating transistor with high-K dielectric sidewall spacer | Leland Chang, Isaac Lauer | 2013-09-17 |
| 8536563 | Nanowire field effect transistors | Sarunya Bangsaruntip, Guy M. Cohen, Shreesh Narasimha | 2013-09-17 |
| 8531871 | 8-transistor SRAM cell design with Schottky diodes | Leland Chang, Isaac Lauer, Chung-Hsun Lin | 2013-09-10 |
| 8526228 | 8-transistor SRAM cell design with outer pass-gate diodes | Leland Chang, Isaac Lauer, Chung-Hsun Lin | 2013-09-03 |
| 8520430 | Nanowire circuits in matched devices | Sarunya Bangsaruntip, Guy M. Cohen, Amlan Majumdar | 2013-08-27 |
| 8519479 | Generation of multiple diameter nanowire field effect transistors | Sarunya Bangsaruntip, Guy M. Cohen | 2013-08-27 |
| 8513099 | Epitaxial source/drain contacts self-aligned to gates for deposited FET channels | Josephine B. Chang, Paul Chang, Vijay Narayanan | 2013-08-20 |
| 8513068 | Nanowire field effect transistors | Sarunya Bangsaruntip, Guy M. Cohen, Shreesh Narasimha | 2013-08-20 |
| 8507892 | Omega shaped nanowire tunnel field effect transistors | Sarunya Bangsaruntip, Josephine B. Chang, Isaac Lauer | 2013-08-13 |
| 8502325 | Metal high-K transistor having silicon sidewalls for reduced parasitic capacitance | Leland Chang, Isaac Lauer, Renee T. Mo | 2013-08-06 |
| 8472239 | Nanowire mesh FET with multiple threshold voltages | Josephine B. Chang, Paul Chang, Michael A. Guillorn | 2013-06-25 |
| 8466451 | Single gate inverter nanowire mesh | Josephine B. Chang, Paul Chang, Michael A. Guillorn | 2013-06-18 |
| 8466012 | Bulk FinFET and SOI FinFET hybrid technology | Josephine B. Chang, Leland Chang, Chung-Hsun Lin | 2013-06-18 |
| 8460991 | Differentially recessed contacts for multi-gate transistor of SRAM cell | Josephine B. Chang, Leland Chang, Chung-Hsun Lin | 2013-06-11 |