Issued Patents All Time
Showing 51–75 of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6931493 | Implementation of an LRU and MRU algorithm in a partitioned cache | Charles Ray Johns, Peichun Peter Liu | 2005-08-16 |
| 6907477 | Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors | Erik R. Altman, Peter G. Capek, Michael K. Gschwind, Harm Peter Hofstee, Ravi Nair +2 more | 2005-06-14 |
| 6848044 | Circuits and methods for recovering link stack data upon branch instruction mis-speculation | Lee Evan Eisen, Balaram Sinharoy, William J. Starke | 2005-01-25 |
| 6820143 | On-chip data transfer in multi-processor system | Michael Norman Day, Charles Ray Johns, Peichun Peter Liu, David Shippy, Thuong Quang Truong | 2004-11-16 |
| 6785841 | Processor with redundant logic | Chekib Akrout, Harm Peter Hofstee | 2004-08-31 |
| 6779049 | Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism | Erik R. Altman, Peter G. Capek, Michael K. Gschwind, Harm Peter Hofstee, Ravi Nair +4 more | 2004-08-17 |
| 6766442 | Processor and method that predict condition register-dependent conditional branch instructions utilizing a potentially stale condition register value | Charles Roberts Moore | 2004-07-20 |
| 6728866 | Partitioned issue queue and allocation strategy | Charles Roberts Moore | 2004-04-27 |
| 6725354 | Shared execution unit in a dual core processor | Charles Roberts Moore | 2004-04-20 |
| 6697939 | Basic block cache microprocessor with instruction history information | — | 2004-02-24 |
| 6678820 | Processor and method for separately predicting conditional branches dependent on lock acquisition | Charles Roberts Moore | 2004-01-13 |
| 6662360 | Method and system for software control of hardware branch prediction mechanism in a data processor | Robert William Hay, Brian R. Konigsburg, David S. Levitan, Balaram Sinharoy | 2003-12-09 |
| 6662294 | Converting short branches to predicated instructions | Charles Roberts Moore | 2003-12-09 |
| 6658558 | Branch prediction circuit selector with instruction context related condition type determining | Charles Roberts Moore | 2003-12-02 |
| 6658555 | Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline | Hung Q. Le, Charles Roberts Moore, David Shippy, Larry Edward Thatcher | 2003-12-02 |
| 6654869 | Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handling | Hung Q. Le, Charles Roberts Moore | 2003-11-25 |
| 6631463 | Method and apparatus for patching problematic instructions in a microprocessor using software interrupts | Michael Stephen Floyd, Hung Q. Le, John Anthony Moore, Kevin F. Reick, Edward John Silha | 2003-10-07 |
| 6629233 | Secondary reorder buffer microprocessor | — | 2003-09-30 |
| 6609190 | Microprocessor with primary and secondary issue queue | Charles Roberts Moore | 2003-08-19 |
| 6574712 | Software prefetch system and method for predetermining amount of streamed data | Michael John Mayfield, Francis Patrick O'Connell, David Scott Ray, Edward John Silha, Joel M. Tendler | 2003-06-03 |
| 6543002 | Recovery from hang condition in a microprocessor | Hung Q. Le, Kevin F. Reick, David Shippy, Larry Edward Thatcher | 2003-04-01 |
| 6543003 | Method and apparatus for multi-stage hang recovery in an out-of-order microprocessor | Michael Stephen Floyd, Hung Q. Le, Larry Scott Leitner, Kevin F. Reick | 2003-04-01 |
| 6539500 | System and method for tracing | Alexander Erik Mericas, Kevin F. Reick, Joel M. Tendler | 2003-03-25 |
| 6477635 | Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing | George McNeil Lattimore, Jose Angel Paredes, Larry Edward Thatcher | 2002-11-05 |
| 6473850 | System and method for handling instructions occurring after an ISYNC instruction | Hoichi Cheong, R. Hay, Hung Q. Le | 2002-10-29 |