Issued Patents All Time
Showing 76–100 of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6460115 | System and method for prefetching data to multiple levels of cache including selectively using a software hint to override a hardware prefetch mechanism | Michael John Mayfield, Francis Patrick O'Connell, David Scott Ray, Edward John Silha, Joel M. Tendler | 2002-10-01 |
| 6430678 | Scoreboard mechanism for serialized string operations utilizing the XER | Hung Q. Le, Lee Evan Eisen, John Edward Derrick, Robert William Hay | 2002-08-06 |
| 6298436 | Method and system for performing atomic memory accesses in a processor system | Hung Q. Le, Larry Edward Thatcher, David Shippy | 2001-10-02 |
| 6212542 | Method and system for executing a program within a multiscalar processor by processing linked thread descriptors | Soummya Mallick, Robert G. McDonald, Edward L. Swarthout | 2001-04-03 |
| 6209081 | Method and system for nonsequential instruction dispatch and execution in a superscalar processor system | Donald E. Waldecker | 2001-03-27 |
| 5995743 | Method and system for interrupt handling during emulation in a data processing system | Soummya Mallick | 1999-11-30 |
| 5978896 | Method and system for increased instruction dispatch efficiency in a superscalar processor system | Chin-Cheng Kau, David S. Levitan, Aubrey Deene Ogden | 1999-11-02 |
| 5956495 | Method and system for processing branch instructions during emulation in a data processing system | Soummya Mallick | 1999-09-21 |
| 5930484 | Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access | Cang Ngoc Tran | 1999-07-27 |
| 5926628 | Selectable priority bus arbitration scheme | Cang Ngoc Tran | 1999-07-20 |
| 5913925 | Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order | Soummya Mallick, Robert G. McDonald | 1999-06-22 |
| 5913044 | Method and system for simultaneous variable-width bus access in a multiprocessor system | Cang Ngoc Tran | 1999-06-15 |
| 5901294 | Method and system for bus arbitration in a multiprocessor system utilizing simultaneous variable-width bus access | Cang Ngoc Tran | 1999-05-04 |
| 5898864 | Method and system for executing a context-altering instruction without performing a context-synchronization operation within high-performance processors | Robert T. Golla, Albert J. Loper, Soummya Mallick | 1999-04-27 |
| 5898882 | Method and system for enhanced instruction dispatch in a superscalar processor system utilizing independently accessed intermediate storage | Chin-Cheng Kau, Aubrey Deene Ogden, Ali A. Poursepanj, Paul Kang-Guo Tu, Donald E. Waldecker | 1999-04-27 |
| 5870575 | Indirect unconditional branches in data processing system emulation mode | Soummya Mallick | 1999-02-09 |
| 5867684 | Method and processor that permit concurrent execution of a store multiple instruction and a dependent instruction | Albert J. Loper, Soummya Mallick, Aubrey Deene Ogden | 1999-02-02 |
| 5812823 | Method and system for performing an emulation context save and restore that is transparent to the operating system | Soummya Mallick, Arturo Martin-de-Nicolas | 1998-09-22 |
| 5802386 | Latency-based scheduling of instructions in a superscalar processor | Soummya Mallick, Robert G. McDonald | 1998-09-01 |
| 5764969 | Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization | Albert J. Loper, Soummya Mallick, Aubrey Deene Ogden, John V. Sell | 1998-06-09 |
| 5764942 | Method and system for selective serialization of instruction processing in a superscalar processor system | Chin-Cheng Kau, Aubrey Deene Ogden, Ali A. Poursepanj, Paul Kang-Guo Tu, Donald E. Waldecker | 1998-06-09 |
| 5761473 | Method and system for increased instruction synchronization efficiency in a superscalar processsor system utilizing partial data dependency interlocking | Chin-Cheng Kau | 1998-06-02 |
| 5758120 | Method and system for increased system memory concurrency in a multi-processor computer system utilizing concurrent access of reference and change bits | John Stephen Muhich, Richard R. Oehler, Edward John Silha | 1998-05-26 |
| 5758140 | Method and system for emulating instructions by performing an operation directly using special-purpose register contents | Soummya Mallick | 1998-05-26 |
| 5758141 | Method and system for selective support of non-architected instructions within a superscaler processor system utilizing a special access bit within a machine state register | Albert J. Loper, Soummya Mallick, Aubrey Deene Ogden, John V. Sell | 1998-05-26 |