Issued Patents All Time
Showing 76–100 of 150 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10672872 | Self-aligned base contacts for vertical fin-type bipolar junction transistors | Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim | 2020-06-02 |
| 10658495 | Vertical fin type bipolar junction transistor (BJT) device with a self-aligned base contact | Choonghyun Lee, Soon-Cheon Seo, Sungjae Lee | 2020-05-19 |
| 10658589 | Alignment through topography on intermediate component for memory device patterning | Hao Tang, Michael Rizzolo, Theodorus E. Standaert | 2020-05-19 |
| 10629721 | Contact resistance reduction for advanced technology nodes | Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2020-04-21 |
| 10615257 | Patterning method for nanosheet transistors | Balasubramanian Pranatharthiharan, Wei Wang, Kevin W. Brew | 2020-04-07 |
| 10608114 | Vertical nano-wire complimentary metal-oxide-semiconductor transistor with cylindrical III-V compound and germanium channel | Choonghyun Lee, Soon-Cheon Seo | 2020-03-31 |
| 10600606 | Vertical vacuum channel transistor with minimized air gap between tip and gate | Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim | 2020-03-24 |
| 10593771 | Vertical fin-type bipolar junction transistor with self-aligned base contact | Choonghyun Lee, Seyoung Kim, Soon-Cheon Seo | 2020-03-17 |
| 10573808 | Phase change memory with a dielectric bi-layer | Iqbal Rashid Saraf, Kevin W. Brew, Nicole Saulnier, Robert L. Bruce | 2020-02-25 |
| 10559654 | Nanosheet isolation for bulk CMOS non-planar devices | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2020-02-11 |
| 10541329 | Boosted vertical field-effect transistor | Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim | 2020-01-21 |
| 10505111 | Confined phase change memory with double air gap | Balasubramanian Pranatharthiharan, Wei Wang | 2019-12-10 |
| 10490454 | Minimize middle-of-line contact line shorts | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2019-11-26 |
| 10468498 | Vertical fin bipolar junction transistor with high germanium content silicon germanium base | Seyoung Kim, Choonghyun Lee, Soon-Cheon Seo | 2019-11-05 |
| 10453844 | Techniques for enhancing vertical gate-all-around FET performance | Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim | 2019-10-22 |
| 10396200 | Method and structure of improving contact resistance for passive and long channel devices | Soon-Cheon Seo, Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2019-08-27 |
| 10396126 | Resistive memory device with electrical gate control | Seyoung Kim, Takashi Ando, Choonghyun Lee, Soon-Cheon Seo | 2019-08-27 |
| 10381074 | Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors | Seyoung Kim, Soon-Cheon Seo, Choonghyun Lee | 2019-08-13 |
| 10381458 | Semiconductor device replacement metal gate with gate cut last in RMG | Andrew M. Greene, Balasubramanian Pranatharthi Haran, Charan V. Surisetty | 2019-08-13 |
| 10361203 | FET trench dipole formation | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2019-07-23 |
| 10355080 | Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2019-07-16 |
| 10347633 | Spacer for trench epitaxial structures | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2019-07-09 |
| 10347456 | Vertical vacuum channel transistor with minimized air gap between tip and gate | Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim | 2019-07-09 |
| 10347632 | Forming spacer for trench epitaxial structures | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2019-07-09 |
| 10332971 | Replacement metal gate stack for diffusion prevention | Takashi Ando, Johnathan E. Faltermeier, Su Chen Fan, Sivananda K. Kanakasabapathy, Tenko Yamashita | 2019-06-25 |