Issued Patents All Time
Showing 51–75 of 150 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10937861 | Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. V. S. Surisetty | 2021-03-02 |
| 10937961 | Structure and method to form bi-layer composite phase-change-memory cell | Myung-Hee Na, Nicole Saulnier, Balasubramanian Pranatharthiharan | 2021-03-02 |
| 10879390 | Boosted vertical field-effect transistor | Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim | 2020-12-29 |
| 10840052 | Planar gate-insulated vacuum channel transistor | Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim | 2020-11-17 |
| 10833269 | 3D phase change memory | Wei Wang, Balasubramanian Pranatharthiharan, Kevin W. Brew | 2020-11-10 |
| 10833267 | Structure and method to form phase change memory cell with self- align top electrode contact | Myung-Hee Na, Nicole Saulnier, Balasubramanian Pranatharthiharan | 2020-11-10 |
| 10833168 | Complementary metal-oxide-semiconductor (CMOS) nanosheet devices with epitaxial source/drains and replacement metal gate structures | Soon-Cheon Seo, Choonghyun Lee | 2020-11-10 |
| 10832941 | Airgap isolation for backend embedded memory stack pillar arrays | Soon-Cheon Seo, Alexander Reznicek, Choonghyun Lee | 2020-11-10 |
| 10818753 | VTFET having a V-shaped groove at the top junction region | Choonghyun Lee, Alexander Reznicek, Soon-Cheon Seo | 2020-10-27 |
| 10804165 | Source and drain isolation for CMOS nanosheet with one block mask | Soon-Cheon Seo, Choonghyun Lee | 2020-10-13 |
| 10803933 | Self-aligned high density and size adjustable phase change memory | Myung-Hee Na, Nicole Saulnier, Balasubramanian Pranatharthiharan | 2020-10-13 |
| 10804159 | Minimize middle-of-line contact line shorts | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2020-10-13 |
| 10790395 | finFET with improved nitride to fin spacing | Ruilong Xie, Chanro Park, Min Gyu Sung | 2020-09-29 |
| 10790284 | Spacer for trench epitaxial structures | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. V. S. Surisetty | 2020-09-29 |
| 10777648 | Vertical fin-type bipolar junction transistor with self-aligned base contact | Choonghyun Lee, Seyoung Kim, Soon-Cheon Seo | 2020-09-15 |
| 10777679 | Removal of work function metal wing to improve device yield in vertical FETs | Choonghyun Lee, Soon-Cheon Seo, Alexander Reznicek | 2020-09-15 |
| 10763326 | Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. V. S. Surisetty | 2020-09-01 |
| 10763431 | Film stress control for memory device stack | Choonghyun Lee, Chih-Chao Yang, Seyoung Kim, Soon-Cheon Seo | 2020-09-01 |
| 10748962 | Method and structure for forming MRAM device | Soon-Cheon Seo, Seyoung Kim, Choonghyun Lee, Kisup Chung | 2020-08-18 |
| 10741756 | Phase change memory with a patterning scheme for tantalum nitride and silicon nitride layers | Nicole Saulnier, Iqbal Rashid Saraf, Kevin W. Brew | 2020-08-11 |
| 10741559 | Spacer for trench epitaxial structures | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. V. S. Surisetty | 2020-08-11 |
| 10734490 | Bipolar junction transistor (BJT) with 3D wrap around emitter | Choonghyun Lee, Shogo Mochizuki, Soon-Cheon Seo | 2020-08-04 |
| 10699951 | Self-aligned low dielectric constant gate cap and a method of forming the same | Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty | 2020-06-30 |
| 10693059 | MTJ stack etch using IBE to achieve vertical profile | Soon-Cheon Seo, Kisup Chung, Seyoung Kim, Choonghyun Lee | 2020-06-23 |
| 10672643 | Reducing off-state leakage current in Si/SiGe dual channel CMOS | Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim | 2020-06-02 |