Issued Patents All Time
Showing 126–150 of 150 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9768173 | Semiconductor structure containing low-resistance source and drain contacts | Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2017-09-19 |
| 9728462 | Stable multiple threshold voltage devices on replacement metal gate CMOS devices | Su Chen Fan, Sivananda K. Kanakasabapathy, Tenko Yamashita | 2017-08-08 |
| 9704760 | Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2017-07-11 |
| 9698101 | Self-aligned local interconnect technology | Andrew M. Greene, Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty, Ruilong Xie | 2017-07-04 |
| 9685340 | Stable contact on one-sided gate tie-down structure | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2017-06-20 |
| 9673101 | Minimize middle-of-line contact line shorts | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2017-06-06 |
| 9627382 | CMOS NFET and PFET comparable spacer width | Kangguo Cheng, Soon-Cheon Seo | 2017-04-18 |
| 9627322 | Semiconductor device having reduced contact resistance | Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2017-04-18 |
| 9595592 | Forming dual contact silicide using metal multi-layer and ion beam mixing | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2017-03-14 |
| 9583584 | Methods for producing integrated circuits using long and short regions and integrated circuits produced from such methods | Chanro Park | 2017-02-28 |
| 9564370 | Effective device formation for advanced technology nodes with aggressive fin-pitch scaling | Sanjay C. Mehta, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2017-02-07 |
| 9536791 | Stable multiple threshold voltage devices on replacement metal gate CMOS devices | Su Chen Fan, Sivananda K. Kanakasabapathy, Tenko Yamashita | 2017-01-03 |
| 9520500 | Self heating reduction for analog radio frequency (RF) device | Balasubramanian Pranatharthiharan, Charan V. Surisetty, Soon-Cheon Seo, Tenko Yamashita | 2016-12-13 |
| 9508816 | Low resistance replacement metal gate structure | Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2016-11-29 |
| 9484401 | Capacitance reduction for advanced technology nodes | Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2016-11-01 |
| 9461168 | Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2016-10-04 |
| 9431486 | Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2016-08-30 |
| 9406568 | Semiconductor structure containing low-resistance source and drain contacts | Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2016-08-02 |
| 9397006 | Co-integration of different fin pitches for logic and analog devices | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2016-07-19 |
| 9337094 | Method of forming contact useful in replacement metal gate processing and related semiconductor structure | Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2016-05-10 |
| 9330983 | CMOS NFET and PFET comparable spacer width | Kangguo Cheng, Soon-Cheon Seo | 2016-05-03 |
| 9312136 | Replacement metal gate stack for diffusion prevention | Takashi Ando, Johnathan E. Faltermeier, Su Chen Fan, Sivananda K. Kanakasabapathy, Tenko Yamashita | 2016-04-12 |
| 9305923 | Low resistance replacement metal gate structure | Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2016-04-05 |
| 9275901 | Semiconductor device having reduced contact resistance | Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2016-03-01 |
| 8183104 | Method for dual-channel nanowire FET device | Christopher C. Hobbs, Kerem Akarvardar | 2012-05-22 |