Issued Patents All Time
Showing 51–74 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6593617 | Field effect transistors with vertical gate side walls and method for making such transistors | Diane C. Boyd, Stuart M. Burns, Yuan Taur, William C. Wille | 2003-07-15 |
| 6562713 | Method of protecting semiconductor areas while exposing a gate | Michael P. Belyansky, Omer H. Dokumaci, Bruce B. Doris | 2003-05-13 |
| 6461529 | Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme | Diane C. Boyd, Stuart M. Burns, Waldemar Walter Kocon, William C. Wille, Richard S. Wise | 2002-10-08 |
| 6440808 | Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-poly | Diane C. Boyd, Stephen Bruce Brodsky, Ronnen Andrew Roy | 2002-08-27 |
| 6353249 | MOSFET with high dielectric constant gate insulator and minimum overlap capacitance | Diane C. Boyd, Meikei Ieong, Wesley C. Natzle | 2002-03-05 |
| 6337497 | Common source transistor capacitor stack | Arvind Kumar, Matthew R. Wordeman | 2002-01-08 |
| 6271094 | Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance | Diane C. Boyd, Meikei Ieong, Wesley C. Natzle | 2001-08-07 |
| 6258679 | Sacrificial silicon sidewall for damascene gate formation | Stuart M. Burns | 2001-07-10 |
| 6245619 | Disposable-spacer damascene-gate process for SUB 0.05 .mu.m MOS devices | Diane C. Boyd, Wesley C. Natzle | 2001-06-12 |
| 6218236 | Method of forming a buried bitline in a vertical DRAM device | Laertis Economikos, Thomas S. Kanarsky, Cheruvu Murthy | 2001-04-17 |
| 6143635 | Field effect transistors with improved implants and method for making such transistors | Diane C. Boyd, Stuart M. Burns, Yuan Taur, William C. Wille | 2000-11-07 |
| 6093947 | Recessed-gate MOSFET with out-diffused source/drain extension | Young Hoon Lee, Hsingjen Wann | 2000-07-25 |
| 6077745 | Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array | Stuart M. Burns, Jeffrey J. Welser, Waldemar Walter Kocon, Howard L. Kalter | 2000-06-20 |
| 6063699 | Methods for making high-aspect ratio holes in semiconductor and its application to a gate damascene process for sub- 0.05 micron mosfets | Young Hoon Lee, Hsingjen Wann | 2000-05-16 |
| 6040210 | 2F-square memory cell for gigabit memory applications | Stuart M. Burns | 2000-03-21 |
| 6040214 | Method for making field effect transistors having sub-lithographic gates with vertical side walls | Diane C. Boyd, Stuart M. Burns, Yuan Taur, William C. Wille | 2000-03-21 |
| 6034389 | Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array | Stuart M. Burns, Howard L. Kalter, Jeffrey J. Welser, Waldemar Walter Kocon | 2000-03-07 |
| 6033957 | 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation | Stuart M. Burns, Jeffrey J. Welser, Waldemar Walter Kocon | 2000-03-07 |
| 6013548 | Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array | Stuart M. Burns, Howard L. Kalter, Jeffrey J. Welser, Waldemar Walter Kocon | 2000-01-11 |
| 5929477 | Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array | Stuart McAllister Burns, Jr., Jeffrey J. Welser, Waldemar Walter Kocon, Howard L. Kalter | 1999-07-27 |
| 5895273 | Silicon sidewall etching | Stuart M. Burns, Waldemar Walter Kocon, Jeffrey J. Welser | 1999-04-20 |
| 5874760 | 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation | Stuart M. Burns, Jeffrey J. Welser, Waldemar Walter Kocon | 1999-02-23 |
| 5759920 | Process for making doped polysilicon layers on sidewalls | Stuart M. Burns, Waldemar Walter Kocon | 1998-06-02 |
| 5206544 | CMOS off-chip driver with reduced signal swing and reduced power supply disturbance | Chih-Liang Chen, Robert H. Dennard | 1993-04-27 |