Issued Patents All Time
Showing 26–50 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7479684 | Field effect transistor including damascene gate with an internal spacer structure | Supratik Guha, Rajarao Jammy, Paul M. Solomon | 2009-01-20 |
| 7476946 | Backgated FinFET having different oxide thicknesses | Andres Bryant, Omer H. Dokumaci, Edward J. Nowak | 2009-01-13 |
| 7442612 | Nitride-encapsulated FET (NNCFET) | Kevin K. Chan, Paul M. Solomon | 2008-10-28 |
| 7435636 | Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods | — | 2008-10-14 |
| 7273785 | Method to control device threshold of SOI MOSFET's | Robert H. Dennard, Wilfried E. Haensch | 2007-09-25 |
| 7271453 | Buried biasing wells in FETS | Edward J. Nowak | 2007-09-18 |
| 7214972 | Strained silicon-channel MOSFET using a damascene gate process | David J. Frank, Kevin K. Chan | 2007-05-08 |
| 7187042 | Backgated FinFET having different oxide thicknesses | Andres Bryant, Omer H. Dokumaci, Edward J. Nowak | 2007-03-06 |
| 7176534 | Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch | Wesley C. Natzle | 2007-02-13 |
| 7166521 | SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layer | Diane C. Boyd, Erin C. Jones, Dominic J. Schepis, Leathen Shi | 2007-01-23 |
| 7089515 | Threshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power | Robert H. Dennard, Wilfried E. Haensch | 2006-08-08 |
| 7078773 | Nitride-encapsulated FET (NNCFET) | Kevin K. Chan, Paul M. Solomon | 2006-07-18 |
| 7056773 | Backgated FinFET having different oxide thicknesses | Andres Bryant, Omer H. Dokumaci, Edward J. Nowak | 2006-06-06 |
| 7018873 | Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate | Robert H. Dennard, Wilfried E. Haensch | 2006-03-28 |
| 6916694 | Strained silicon-channel MOSFET using a damascene gate process | David J. Frank, Kevin K. Chan | 2005-07-12 |
| 6841831 | Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process | Diane C. Boyd, Kevin K. Chan, Wesley C. Natzle, Leathen Shi | 2005-01-11 |
| 6835614 | Damascene double-gate MOSFET with vertical channel regions | Jeffrey J. Brown, Wesley C. Natzle | 2004-12-28 |
| 6835633 | SOI wafers with 30-100 å buried oxide (BOX) created by wafer bonding using 30-100 å thin oxide as bonding layer | Diane C. Boyd, Erin C. Jones, Dominic J. Schepis, Leathen Shi | 2004-12-28 |
| 6815296 | Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control | Robert H. Dennard, Wilfried E. Haensch | 2004-11-09 |
| 6812527 | Method to control device threshold of SOI MOSFET's | Robert H. Dennard, Wilfried E. Haensch | 2004-11-02 |
| 6686630 | Damascene double-gate MOSFET structure and its fabrication method | Erin C. Jones, Cheruvu Murthy, Philip J. Oldiges, Leathen Shi | 2004-02-03 |
| 6664598 | Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control | Robert H. Dennard, Wilfried E. Haensch | 2003-12-16 |
| 6660598 | Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region | Diane C. Boyd, Kevin K. Chan, Wesley C. Natzle, Leathen Shi | 2003-12-09 |
| 6656824 | Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch | Wesley C. Natzle | 2003-12-02 |
| 6635923 | Damascene double-gate MOSFET with vertical channel regions | Jeffrey J. Brown, Wesley C. Natzle | 2003-10-21 |