Issued Patents All Time
Showing 201–225 of 225 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8835237 | Robust replacement gate integration | Sanjay C. Mehta | 2014-09-16 |
| 8790991 | Method and structure for shallow trench isolation to mitigate active shorts | Jason E. Cummings, Balasubramanian S. Haran, Sanjay C. Mehta | 2014-07-29 |
| 8779515 | Semiconductor structure containing an aluminum-containing replacement gate electrode | Sivananda K. Kanakasabapathy, David V. Horak | 2014-07-15 |
| 8753934 | Structure and method to integrate embedded DRAM with FinFET | Sivananda K. Kanakasabapathy, Geng Wang | 2014-06-17 |
| 8748991 | Control of flatband voltages and threshold voltages in high-k metal gate stacks and structures for CMOS devices | Takashi Ando, Vijay Narayanan | 2014-06-10 |
| 8741757 | Replacement gate electrode with multi-thickness conductive metallic nitride layers | Vamsi K. Paruchuri | 2014-06-03 |
| 8722548 | Structures and techniques for atomic layer deposition | Shintaro Aoyama, Robert D. Clark, Steven P. Consiglio, Marinus Hopstaken, Paul C. Jamison +4 more | 2014-05-13 |
| 8679941 | Method to improve wet etch budget in FEOL integration | Jason E. Cummings, Lisa F. Edge, Balasubramanian S. Haran, David V. Horak, Sanjay C. Mehta | 2014-03-25 |
| 8680629 | Control of flatband voltages and threshold voltages in high-k metal gate stacks and structures for CMOS devices | Takashi Ando, Vijay Narayanan | 2014-03-25 |
| 8653610 | High performance non-planar semiconductor devices with metal filled inter-fin gaps | Sivananda K. Kanakasabapathy | 2014-02-18 |
| 8614486 | Low resistance source and drain extensions for ETSOI | Balasubramanian S. Haran, Sivananda K. Kanakasabapathy, Sanjay C. Mehta | 2013-12-24 |
| 8541275 | Single metal gate CMOS integration by intermixing polarity specific capping layers | Sivananda K. Kanakasabapathy, Matthew W. Copel | 2013-09-24 |
| 8486778 | Low resistance source and drain extensions for ETSOI | Balasubramanian S. Haran, Sivananda K. Kanakasabapathy, Sanjay C. Mehta | 2013-07-16 |
| 8421139 | Structure and method to integrate embedded DRAM with finfet | Sivananda K. Kanakasabapathy, Geng Wang | 2013-04-16 |
| 8394684 | Structure and method for stress latching in non-planar semiconductor devices | Sivananda K. Kanakasabapathy, Sanjay C. Mehta | 2013-03-12 |
| 8368146 | FinFET devices | Veeraraghavan S. Basker, David V. Horak, Charles W. Koburger, III | 2013-02-05 |
| 8309447 | Method for integrating multiple threshold voltage devices for CMOS | Kangguo Cheng, Bruce B. Doris, Lisa F. Edge, Balasubramanian S. Haran, Ali Khakifirooz +1 more | 2012-11-13 |
| 8304836 | Structure and method to obtain EOT scaled dielectric stacks | Takashi Ando, Lisa F. Edge, Sufi Zafar, Changhwan Choi, Paul C. Jamison +2 more | 2012-11-06 |
| 8274116 | Control of threshold voltages in high-k metal gate stack and structures for CMOS devices | Takashi Ando, Vijay Narayanan | 2012-09-25 |
| 8232179 | Method to improve wet etch budget in FEOL integration | Jason E. Cummings, Lisa F. Edge, Balasubramanian S. Haran, David V. Horak, Sanjay C. Mehta | 2012-07-31 |
| 8133746 | Method for semiconductor gate hardmask removal and decoupling of implants | Sivananda K. Kanakasabapathy | 2012-03-13 |
| 8124485 | Molecular spacer layer for semiconductor oxide surface and high-K dielectric stack | Dario L. Goldfarb, Dirk Pfeiffer | 2012-02-28 |
| 7943458 | Methods for obtaining gate stacks with tunable threshold voltage and scaling | Sivananda K. Kanakasabapathy, Matthew W. Copel | 2011-05-17 |
| 7855105 | Planar and non-planar CMOS devices with multiple tuned threshold voltages | Vijay Narayanan, Vamsi K. Paruchuri | 2010-12-21 |
| 6789426 | Microfluidic channels with integrated ultrasonic transducers for temperature measurement and method | Goksen G. Yaralioglu, Arif Sanli Ergun, Butrus T. Khuri-Yakub | 2004-09-14 |