Issued Patents All Time
Showing 301–320 of 320 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6972250 | Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device | Cyril Cabral, Jr., Roy A. Carruthers, Kevin K. Chan, Jack O. Chu, Steven J. Koester +2 more | 2005-12-06 |
| 6967377 | Double-gate fet with planarized surfaces and self-aligned silicides | Hon-Sum Philip Wong | 2005-11-22 |
| 6963505 | Method circuit and system for determining a reference voltage | — | 2005-11-08 |
| 6946696 | Self-aligned isolation double-gate FET | Kevin K. Chan, Meikei Ieong, Ronnen Andrew Roy, Paul M. Solomon, Min Yang | 2005-09-20 |
| 6774015 | Strained silicon-on-insulator (SSOI) and method to form the same | Silke Christiansen | 2004-08-10 |
| 6759710 | Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques | Kevin K. Chan, Yuan Taur, Hon-Sum Philip Wong | 2004-07-06 |
| 6716708 | Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby | Cyril Cabral, Jr., Kevin K. Chan, Kathryn Guarini, Christian Lavoie, Ronnen Andrew Roy +1 more | 2004-04-06 |
| 6713827 | Micro-structures and methods for their manufacture | Steven A. Cordes, Joanna Rosner, Jeannine M. Trewhella | 2004-03-30 |
| 6690072 | Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device | Cyril Cabral, Jr., Roy A. Carruthers, Kevin K. Chan, Jack O. Chu, Steven J. Koester +2 more | 2004-02-10 |
| 6667528 | Semiconductor-on-insulator lateral p-i-n photodetector with a reflecting mirror and backside contact and method for forming the same | Kern Rim, Dennis L. Rogers, Jeremy D. Schaub, Min Yang | 2003-12-23 |
| 6645861 | Self-aligned silicide process for silicon sidewall source and drain contacts | Cyril Cabral, Jr., Kevin K. Chan, Kathryn Guarini, Christian Lavoie, Paul M. Solomon +1 more | 2003-11-11 |
| 6642115 | Double-gate FET with planarized surfaces and self-aligned silicides | Hon-Sum Philip Wong | 2003-11-04 |
| 6562642 | Micro-structures and methods for their manufacture | Steven A. Cordes, Joanna Rosner, Jeannine M. Trewhella | 2003-05-13 |
| 6555880 | Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby | Cyril Cabral, Jr., Kevin K. Chan, Kathryn Guarini, Christian Lavoie, Ronnen Andrew Roy +1 more | 2003-04-29 |
| 6503833 | Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby | Atul Ajmera, Cyril Cabral, Jr., Roy A. Carruthers, Kevin K. Chan, Paul Kozlowski +3 more | 2003-01-07 |
| 6475072 | Method of wafer smoothing for bonding using chemo-mechanical polishing (CMP) | Donald F. Canaperi, Jack O. Chu, Lijuan Huang, John A. Ott, Michael F. Lofaro | 2002-11-05 |
| 6448131 | Method for increasing the capacitance of a trench capacitor | Cyril Cabral, Jr., Kevin K. Chan, Ramachandra Divakaruni, Christian Lavoie, Fenton R. McFeely | 2002-09-10 |
| 6444578 | Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices | Cyril Cabral, Jr., Roy A. Carruthers, Kevin K. Chan, Kathryn Guarini, James M. E. Harper +2 more | 2002-09-03 |
| 6365465 | Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques | Kevin K. Chan, Yuan Taur, Hon-Sum Philip Wong | 2002-04-02 |
| 6300218 | Method for patterning a buried oxide thickness for a separation by implanted oxygen (simox) process | Devendra K. Sadana | 2001-10-09 |