Issued Patents All Time
Showing 251–275 of 320 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7884004 | Maskless process for suspending and thinning nanowires | Sarunya Bangsaruntip, Jeffrey W. Sleight | 2011-02-08 |
| 7864612 | Reading array cell with matched reference cell | Eli Lusky, Boaz Eitan, Eduardo Maayan | 2011-01-04 |
| 7842562 | Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates | — | 2010-11-30 |
| 7816275 | Gate patterning of nano-channel devices | Nicholas C. M. Fuller, Sarunya Bangsaruntip, Sebastian U. Engelmann, Lidija Sekaric, Qingyun Yang +1 more | 2010-10-19 |
| 7811883 | Method of forming a nanowire based non-volatile floating-gate memory | — | 2010-10-12 |
| 7812340 | Strained-silicon-on-insulator single-and double-gate MOSFET and method for forming the same | Patricia M. Mooney | 2010-10-12 |
| 7795677 | Nanowire field-effect transistors | Sarunya Bangsaruntip, Katherine L. Saenger | 2010-09-14 |
| 7749905 | Vertical Fet with nanowire channels and a silicided bottom contact | Paul M. Solomon | 2010-07-06 |
| 7742339 | Rd algorithm improvement for NROM technology | Arik Rizel | 2010-06-22 |
| 7715237 | Method, system and circuit for operating a non-volatile memory array | — | 2010-05-11 |
| 7709352 | In-place bonding of microstructures | Patricia M. Mooney, Vamsi K. Paruchuri | 2010-05-04 |
| 7675782 | Method, system and circuit for programming a non-volatile memory array | Yan Polansky | 2010-03-09 |
| 7659200 | Self-constrained anisotropic germanium nanostructure from electroplating | Qiang Huang, Lubomyr T. Romankiw, Hariklia Deligianni | 2010-02-09 |
| 7585740 | Fully silicided extrinsic base transistor | David C. Ahlgren, Christian Lavoie, Francois Pagette, Anna W. Topol | 2009-09-08 |
| 7572300 | Monolithic high aspect ratio nano-size scanning probe microscope (SPM) tip formed by nanowire growth | Hendrik F. Hamann | 2009-08-11 |
| 7534675 | Techniques for fabricating nanowire field-effect transistors | Sarunya Bangsaruntip, Katherine L. Saenger | 2009-05-19 |
| 7498235 | Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates | Tze-Chiang Chen, Alexander Reznicek, Devendra K. Sadana, Ghavam G. Shahidi | 2009-03-03 |
| 7498640 | Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby | Cyril Cabral, Jr., Kevin K. Chan, Kathryn Guarini, Christian Lavoie, Paul M. Solomon +1 more | 2009-03-03 |
| 7496251 | Apparatus and methods for integrally packaging optoelectronic devices, IC chips and optical transmission lines | Fuad E. Doany, Jeannine M. Trewhella | 2009-02-24 |
| 7476573 | Methods of selective deposition of fine particles onto selected regions of a substrate | — | 2009-01-13 |
| 7456081 | In-place bonding of microstructures | Patricia M. Mooney, Vamsi K. Paruchuri | 2008-11-25 |
| 7457183 | Operating array cells with matched reference cells | Eli Lusky, Boaz Eitan, Eduardo Maayan | 2008-11-25 |
| 7449767 | Mixed orientation and mixed material semiconductor-on-insulator wafer | Alexander Reznicek, Katherine L. Saenger, Min Yang | 2008-11-11 |
| 7446025 | Method of forming vertical FET with nanowire channels and a silicided bottom contact | Paul M. Solomon | 2008-11-04 |
| 7391074 | Nanowire based non-volatile floating-gate memory | — | 2008-06-24 |