Issued Patents All Time
Showing 201–225 of 401 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10777658 | Method and structure of fabricating I-shaped silicon vertical field-effect transistors | Kangguo Cheng, Juntao Li, Peng Xu | 2020-09-15 |
| 10777679 | Removal of work function metal wing to improve device yield in vertical FETs | Soon-Cheon Seo, Injo Ok, Alexander Reznicek | 2020-09-15 |
| 10777659 | Self-aligned bottom source/drain epitaxial growth in vertical field effect transistors | Ruqiang Bao, Shogo Mochizuki, Brent A. Anderson, Hemanth Jagannathan | 2020-09-15 |
| 10777648 | Vertical fin-type bipolar junction transistor with self-aligned base contact | Seyoung Kim, Injo Ok, Soon-Cheon Seo | 2020-09-15 |
| 10770546 | High density nanotubes and nanotube devices | Kangguo Cheng, Juntao Li, Peng Xu | 2020-09-08 |
| 10763431 | Film stress control for memory device stack | Injo Ok, Chih-Chao Yang, Seyoung Kim, Soon-Cheon Seo | 2020-09-01 |
| 10763177 | I/O device for gate-all-around transistors | Jingyun Zhang, Takashi Ando, Alexander Reznicek, Pouya Hashemi | 2020-09-01 |
| 10756176 | Stacked nanosheet technology with uniform Vth control | Pouya Hashemi, Takashi Ando, Jingyun Zhang, Alexander Reznicek | 2020-08-25 |
| 10756175 | Inner spacer formation and contact resistance reduction in nanosheet transistors | Kangguo Cheng, Juntao Li, Shogo Mochizuki | 2020-08-25 |
| 10756170 | VFET devices with improved performance | Kangguo Cheng, Juntao Li, Shogo Mochizuki | 2020-08-25 |
| 10756216 | Nanosheet mosfet with isolated source/drain epitaxy and close junction proximity | Xin Miao, Alexander Reznicek, Jingyun Zhang | 2020-08-25 |
| 10749012 | Formation of self-aligned bottom spacer for vertical transistors | Ruqiang Bao, Hemanth Jagannathan, Shogo Mochizuki | 2020-08-18 |
| 10748994 | Vertically stacked nFET and pFET with dual work function | Alexander Reznicek, Takashi Ando, Jingyun Zhang, Pouya Hashemi | 2020-08-18 |
| 10748962 | Method and structure for forming MRAM device | Soon-Cheon Seo, Seyoung Kim, Injo Ok, Kisup Chung | 2020-08-18 |
| 10748819 | Vertical transport FETs with asymmetric channel profiles using dipole layers | Takashi Ando, Sanghoon Shin, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek | 2020-08-18 |
| 10741677 | Stacked silicon nanotubes | Juntao Li, Kangguo Cheng, Peng Xu | 2020-08-11 |
| 10741652 | Wrap-around-contact structure for top source/drain in vertical FETs | Christopher J. Waskiewicz, Alexander Reznicek, Hemanth Jagannathan | 2020-08-11 |
| 10734490 | Bipolar junction transistor (BJT) with 3D wrap around emitter | Injo Ok, Shogo Mochizuki, Soon-Cheon Seo | 2020-08-04 |
| 10734479 | FinFET CMOS with asymmetric gate threshold voltage | Alexander Reznicek, Takashi Ando, Jingyun Zhang, Pouya Hashemi | 2020-08-04 |
| 10734447 | Field-effect transistor unit cells for neural networks with differential weights | Takashi Ando, Pouya Hashemi, Alexander Reznicek, Jingyun Zhang | 2020-08-04 |
| 10734286 | Multiple dielectrics for gate-all-around transistors | Takashi Ando, Jingyun Zhang, Alexander Reznicek, Pouya Hashemi | 2020-08-04 |
| 10720502 | Vertical transistors having a layer of charge carriers in the extension region for reduced extension region resistance | Takashi Ando, Pouya Hashemi, Alexander Reznicek, Jingyun Zhang | 2020-07-21 |
| 10720364 | Forming vertical transistor devices with greater layout flexibility and packing density | Kangguo Cheng, Juntao Li | 2020-07-21 |
| 10720527 | Transistor having an oxide-isolated strained channel fin on a bulk substrate | Kangguo Cheng, Juntao Li, Peng Xu | 2020-07-21 |
| 10714399 | Gate-last process for vertical transport field-effect transistor | Shogo Mochizuki, Hemanth Jagannathan | 2020-07-14 |