Issued Patents All Time
Showing 76–100 of 757 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10170587 | Heterogeneous source drain region and extension region | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2019-01-01 |
| 10170637 | Perfectly symmetric gate-all-around FET on suspended nanowire | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2019-01-01 |
| 10170550 | Stressed nanowire stack for field effect transistor | Martin M. Frank, Pouya Hashemi, Alexander Reznicek | 2019-01-01 |
| 10170537 | Capacitor structure compatible with nanowire CMOS | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2019-01-01 |
| 10158001 | Heterogeneous source drain region and extension region | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-12-18 |
| 10153157 | P-FET with graded silicon-germanium channel | Kangguo Cheng, Darsen D. Lu, Alexander Reznicek | 2018-12-11 |
| 10147804 | High density vertical nanowire stack for field effect transistor | Kangguo Cheng, Juntao Li | 2018-12-04 |
| 10147602 | Double aspect ratio trapping | Kangguo Cheng, Bruce B. Doris, Alexander Reznicek | 2018-12-04 |
| 10147679 | Electrical fuse and/or resistor structures | Veeraraghavan S. Basker, Kangguo Cheng, Juntao Li | 2018-12-04 |
| 10141428 | Fin formation in fin field effect transistors | Kangguo Cheng, Bruce B. Doris, Hong He, Yunpeng Yin | 2018-11-27 |
| 10141461 | Textured multi-junction solar cell and fabrication method | Bahman Hekmatshoartabari, Ghavam G. Shahidi, Davood Shahrjerdi | 2018-11-27 |
| 10109709 | P-FET with strained silicon-germanium channel | Kangguo Cheng, Alexander Reznicek, Ghavam G. Shahidi | 2018-10-23 |
| 10109361 | Coarse pass and fine pass multi-level NVM programming | Pranav Kalavade, Rohit S. Shenoy, Aliasgar S. Madraswala, Donia Sebastian, Xin Guo | 2018-10-23 |
| 10084090 | Method and structure of stacked FinFET | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-09-25 |
| 10083907 | Method and structure for forming on-chip anti-fuse with reduced breakdown voltage | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-09-25 |
| 10083972 | Hybrid logic and SRAM contacts | Veeraraghavan S. Basker, Kangguo Cheng | 2018-09-25 |
| 10084041 | Method and structure for improving FinFET with epitaxy source/drain | Kangguo Cheng, Alexander Reznicek, Tenko Yamashita | 2018-09-25 |
| 10084050 | Semiconductor device with low-K gate cap and self-aligned contact | Kangguo Cheng, Alexander Reznicek, Charan V. Surisetty | 2018-09-25 |
| 10084067 | FinFET with epitaxial source and drain regions and dielectric isolated channel region | Kangguo Cheng, Ramachandra Divakaruni, Alexander Reznicek, Soon-Cheon Seo | 2018-09-25 |
| 10079303 | Method to form strained nFET and strained pFET nanowires on a same substrate | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-09-18 |
| 10079181 | P-FET with strained silicon-germanium channel | Kangguo Cheng, Alexander Reznicek, Ghavam G. Shahidi | 2018-09-18 |
| 10056474 | Semiconductor structures having increased channel strain using fin release in gate regions | Kangguo Cheng, Bruce B. Doris, Darsen D. Lu, Alexander Reznicek, Kern Rim | 2018-08-21 |
| 10050166 | Silicon heterojunction photovoltaic device with wide band gap emitter | Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi | 2018-08-14 |
| 10049945 | Forming a CMOS with dual strained channels | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-08-14 |
| 10032773 | FinFET with reduced capacitance | Veeraraghavan S. Basker, Kangguo Cheng, Charles W. Koburger, III | 2018-07-24 |