Issued Patents All Time
Showing 151–175 of 1,279 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11315938 | Stacked nanosheet rom | Ruilong Xie, Karthik Balakrishnan, Bahman Hekmatshoartabari | 2022-04-26 |
| 11315923 | Stacked nanosheet inverter | Karthik Balakrishnan, Bahman Hekmatshoartabari | 2022-04-26 |
| 11309216 | Large grain copper interconnect lines for MRAM | Oleg Gluschenkov, Yasir Sulehria, Devika Sil | 2022-04-19 |
| 11302813 | Wrap around contact for nanosheet source drain epitaxy | Xin Miao, Choonghyun Lee, Jingyun Zhang | 2022-04-12 |
| 11302794 | FinFET with dual work function metal | Ruilong Xie, Takashi Ando, Pouya Hashemi | 2022-04-12 |
| 11295983 | Transistor having source or drain formation assistance regions with improved bottom isolation | Ruilong Xie, Effendi Leobandung, Jingyun Zhang | 2022-04-05 |
| 11295988 | Semiconductor FET device with bottom isolation and high-κ first | Ruilong Xie, Julien Frougier, Jingyun Zhang, Takashi Ando | 2022-04-05 |
| 11289484 | Forming source and drain regions for sheet transistors | Jingyun Zhang, Ruilong Xie, Xin Miao | 2022-03-29 |
| 11282947 | Heterojunction bipolar transistor with a silicon oxide layer on a silicon germanium base | Injo Ok, Choonghyun Lee, Soon-Cheon Seo | 2022-03-22 |
| 11276576 | Gate metal patterning to avoid gate stack attack due to excessive wet etching | Junli Wang, Shogo Mochizuki, Joshua M. Rubin | 2022-03-15 |
| 11271108 | Low-noise gate-all-around junction field effect transistor | Bahman Hekmatshoartabari, Karthik Balakrishnan | 2022-03-08 |
| 11271107 | Reduction of bottom epitaxy parasitics for vertical transport field effect transistors | Tao Li, Tsung-Sheng Kang, Ruilong Xie | 2022-03-08 |
| 11270910 | Interconnect structure with partial sidewall liner | Oscar van der Straten | 2022-03-08 |
| 11251304 | Wrap-around bottom contact for bottom source/drain | Junli Wang, Ruilong Xie, Bruce B. Doris | 2022-02-15 |
| 11251301 | Cross-bar vertical transport field effect transistors without corner rounding | Tsung-Sheng Kang, Ruilong Xie, Tao Li | 2022-02-15 |
| 11251185 | Stacked complementary junction FETs for analog electronic circuits | Karthik Balakrishnan, Bahman Hekmatshoartabari, Jeng-Bang Yau | 2022-02-15 |
| 11251094 | Oxygen vacancy passivation in high-k dielectrics for vertical transport field effect transistor | Choonghyun Lee, Takashi Ando, Jingyun Zhang | 2022-02-15 |
| 11245025 | Gate last vertical transport field effect transistor | Choonghyun Lee, Soon-Cheon Seo, Injo Ok | 2022-02-08 |
| 11245009 | Asymmetric channel FinFETs with wrap around channel | Jingyun Zhang | 2022-02-08 |
| 11244864 | Reducing parasitic capacitance within semiconductor devices | Ruilong Xie, Reinaldo Vega, Kangguo Cheng | 2022-02-08 |
| 11239414 | Physical unclonable function for MRAM structures | Ruilong Xie, Oscar van der Straten, Koichi Motoyama | 2022-02-01 |
| 11239359 | Fabricating a gate-all-around (GAA) field effect transistor having threshold voltage asymmetry by thinning source side lateral end portion of the nanosheet layer | Jingyun Zhang, Choonghyun Lee, Takashi Ando, Pouya Hashemi | 2022-02-01 |
| 11239343 | Vertical transistor including symmetrical source/drain extension junctions | Chun-Chen Yeh, Veeraraghavan S. Basker, Junli Wang | 2022-02-01 |
| 11239115 | Partial self-aligned contact for MOL | Ruilong Xie, Veeraraghavan S. Basker, Junli Wang | 2022-02-01 |
| 11233137 | Transistors and methods of forming transistors using vertical nanowires | Dominic J. Schepis | 2022-01-25 |