Issued Patents All Time
Showing 951–975 of 1,279 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9552988 | Tone inverted directed self-assembly (DSA) fin patterning | Hong He, Chi-Chun Liu, Chiahsun Tseng, Tenko Yamashita | 2017-01-24 |
| 9548386 | Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Kern Rim | 2017-01-17 |
| 9548319 | Structure for integration of an III-V compound semiconductor on SOI | Hemanth Jagannathan | 2017-01-17 |
| 9543388 | Complementary metal-oxide silicon having silicon and silicon germanium channels | Gen P. Lauer, Isaac Lauer, Jeffrey W. Sleight | 2017-01-10 |
| 9543323 | Strain release in PFET regions | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Kern Rim | 2017-01-10 |
| 9543302 | Forming IV fins and III-V fins on insulator | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz | 2017-01-10 |
| 9536939 | High density vertically integrated FEOL MIM capacitor | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2017-01-03 |
| 9536736 | Reducing substrate bowing caused by high percentage sige layers | Stephen W. Bedell, Keith E. Fogel, Devendra K. Sadana | 2017-01-03 |
| 9530843 | FinFET having an epitaxially grown semiconductor on the fin in the channel region | Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Davood Shahrjerdi | 2016-12-27 |
| 9530772 | Methods of manufacturing devices including gates with multiple lengths | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2016-12-27 |
| 9530699 | Semiconductor device including gate channel having adjusted threshold voltage | Pranita Kerber, Qiqing C. Ouyang | 2016-12-27 |
| 9530669 | Method of making a semiconductor device having a semiconductor material on a relaxed semiconductor including replacing a strained, selective etchable material, with a low density dielectric in a cavity | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2016-12-27 |
| 9525027 | Lateral bipolar junction transistor having graded SiGe base | Pouya Hashemi, Ali Khakifirooz, Darsen D. Lu, Dominic J. Schepis | 2016-12-20 |
| 9525064 | Channel-last replacement metal-gate vertical field effect transistor | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2016-12-20 |
| 9524969 | Integrated circuit having strained fins on bulk substrate | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2016-12-20 |
| 9524882 | Contact structure and extension formation for III-V nFET | Veeraraghavan S. Basker | 2016-12-20 |
| 9520397 | Abrupt source/drain junction formation using a diffusion facilitation layer | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz | 2016-12-13 |
| 9520469 | Fabrication of fin structures having high germanium content | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2016-12-13 |
| 9520394 | Contact structure and extension formation for III-V nFET | Veeraraghavan S. Basker | 2016-12-13 |
| 9520328 | Type III-V and type IV semiconductor device formation | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz | 2016-12-13 |
| 9515194 | Nano-ribbon channel transistor with back-bias control | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2016-12-06 |
| 9515173 | Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz | 2016-12-06 |
| 9515073 | III-V semiconductor CMOS FinFET device | Hemanth Jagannathan, Devendra K. Sadana, Charan V. Surisetty | 2016-12-06 |
| 9514997 | Silicon-germanium FinFET device with controlled junction | Kangguo Cheng, Pouya Hashemi, Kam-Leung Lee | 2016-12-06 |
| 9514995 | Implant-free punch through doping layer formation for bulk FinFET structures | Keith E. Fogel, Devendra K. Sadana, Dominic J. Schepis | 2016-12-06 |