Issued Patents All Time
Showing 76–100 of 365 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8704343 | Borderless interconnect line structure self-aligned to upper and lower level contact vias | Shom Ponoth, Charles W. Koburger, III, Chih-Chao Yang | 2014-04-22 |
| 8703604 | Creation of vias and trenches with different depths | Shom Ponoth, Takeshi Nogami, Chih-Chao Yang | 2014-04-22 |
| 8697561 | Microelectronic structure by selective deposition | Toshiharu Furukawa, Steven J. Holmes, Charles W. Koburger, III | 2014-04-15 |
| 8679968 | Method for forming a self-aligned contact opening by a lateral etch | Ruilong Xie, Su Chen Fan, Pranatharthiharan Haran Balasubramanian, Ponoth Shom | 2014-03-25 |
| 8679941 | Method to improve wet etch budget in FEOL integration | Jason E. Cummings, Lisa F. Edge, Balasubramanian S. Haran, Hemanth Jagannathan, Sanjay C. Mehta | 2014-03-25 |
| 8679909 | Recessing and capping of gate structures with varying metal compositions | Ruilong Xie, Su Chen Fan, Pranatharthiharan Haran Balasubramanian | 2014-03-25 |
| 8637908 | Borderless contacts in semiconductor devices | Su Chen Fan, Sivananda K. Kanakasabapathy | 2014-01-28 |
| 8637400 | Interconnect structures and methods for back end of the line integration | Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang | 2014-01-28 |
| 8629511 | Mask free protection of work function material portions in wide replacement gate electrodes | Charles W. Koburger, III, Marc A. Bergendahl, Shom Ponoth, Chih-Chao Yang | 2014-01-14 |
| 8629008 | Electrical isolation structures for ultra-thin semiconductor-on-insulator devices | Balasubramanian S. Haran, Charles W. Koburger, III, Shom Ponoth | 2014-01-14 |
| 8623730 | Method for fabricating silicon-on-insulator transistor with self-aligned borderless source/drain contacts | Susan S. Fan, Balasubramanian S. Haran, Charles W. Koburger, III | 2014-01-07 |
| 8609534 | Electrical fuse structure and method of fabricating same | Chih-Chao Yang, Charles W. Koburger, III, Shom Ponoth | 2013-12-17 |
| 8569168 | Dual-metal self-aligned wires and vias | Steven J. Holmes, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang | 2013-10-29 |
| 8568604 | CMOS gate structures fabricated by selective oxidation | Bruce B. Doris, Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, Charles W. Koburger, III | 2013-10-29 |
| 8558284 | Integrated circuit line with electromigration barriers | Takeshi Nogami, Shom Ponoth, Chih-Chao Yang | 2013-10-15 |
| 8541823 | Field effect transistor | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, Charles W. Koburger, III | 2013-09-24 |
| 8525339 | Hybrid copper interconnect structure and method of fabricating same | Chih-Chao Yang, Charles W. Koburger, III, Shom Ponoth | 2013-09-03 |
| 8518773 | Method of fabricating semiconductor capacitor | Shom Ponoth, Hosadurga Shobha, Chih-Chao Yang | 2013-08-27 |
| 8512458 | Chemical and particulate filters containing chemically modified carbon nanotube structures | Steven J. Holmes, Mark C. Hakey, James G. Ryan | 2013-08-20 |
| 8507187 | Multi-exposure lithography employing a single anti-reflective coating layer | Veeraraghavan S. Basker, Willard E. Conley, Steven J. Holmes | 2013-08-13 |
| 8492274 | Metal alloy cap integration | Chih-Chao Yang, Marc A. Bergendahl, Steven J. Holmes, Charles W. Koburger, III, Shom Ponoth | 2013-07-23 |
| 8492270 | Structure for nano-scale metallization and method for fabricating same | Shom Ponoth, Elbert E. Huang, Sivananda K. Kanakasabapathy, Charles W. Koburger, III, Chih-Chao Yang | 2013-07-23 |
| 8492265 | Pad bonding employing a self-aligned plated liner for adhesion enhancement | Chih-Chao Yang, Takeshi Nogami, Shom Ponoth | 2013-07-23 |
| 8482132 | Pad bonding employing a self-aligned plated liner for adhesion enhancement | Chih-Chao Yang, Takeshi Nogami, Shom Ponoth | 2013-07-09 |
| 8476160 | Sublithographic patterning employing image transfer of a controllably damaged dielectric sidewall | Shom Ponoth, Chih-Chao Yang | 2013-07-02 |