Issued Patents All Time
Showing 51–75 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6862221 | Memory device having a thin top dielectric and method of erasing same | Ashot Melik-Martirosian, Sameer Haddad | 2005-03-01 |
| 6861307 | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same | Wei Zheng, Nicholas H. Tripsas, Zoran Krivokapic, Jack F. Thomas, Mark T. Ramsbey | 2005-03-01 |
| 6855608 | Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance | Mark T. Ramsbey, Jean Y. Yang, Hiroyuki Kinoshita, Cyrus E. Tabery, Jeff P. Erhardt +3 more | 2005-02-15 |
| 6834012 | Memory device and methods of using negative gate stress to correct over-erased memory cells | Yi He, Edward Franklin Runnion, Zhizheng Liu, Zengtao T. Liu | 2004-12-21 |
| 6822909 | Method of controlling program threshold voltage distribution of a dual cell memory device | Darlene Hamilton, Edward Hsia, Edward Franklin Runnion, Kulachet Tanpairoj | 2004-11-23 |
| 6813752 | Method of determining charge loss activation energy of a memory array | Edward Hsia, Darlene Hamilton, Wei Zheng, Kulachet Tanpairoj | 2004-11-02 |
| 6795357 | Method for reading a non-volatile memory cell | Zhizheng Liu, Yi He, Sameer Haddad | 2004-09-21 |
| 6795342 | System for programming a non-volatile memory cell | Yi He, Zhizheng Liu, Sameer Haddad | 2004-09-21 |
| 6788583 | Pre-charge method for reading a non-volatile memory cell | Yi He, Edward Franklin Runnion, Zhizheng Liu, Darlene Hamilton, Pauling Chen +1 more | 2004-09-07 |
| 6770938 | Diode fabrication for ESD/EOS protection | Michael Fliesler, Mark T. Ramsbey, Ian Morgan, Timothy Thurgate, Paohua Kuo +1 more | 2004-08-03 |
| 6771545 | Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array | Edward Hsia, Eric M. Ajimine, Darlene Hamilton, Pauling Chen, Ming-Huei Shieh +2 more | 2004-08-03 |
| 6768160 | Non-volatile memory cell and method of programming for improved data retention | Yu-Chuan Li, Zhizheng Liu | 2004-07-27 |
| 6750103 | NROM cell with N-less channel | Masaaki Higashitani | 2004-06-15 |
| 6743677 | Method for fabricating nitride memory cells using a floating gate fabrication process | Darlene Hamilton, Binh Quang Le, Wei Zheng | 2004-06-01 |
| 6744675 | Program algorithm including soft erase for SONOS memory device | Wei Zheng | 2004-06-01 |
| 6740926 | Planar transistor structure using isolation implants for improved Vss resistance and for process simplification | — | 2004-05-25 |
| 6735114 | Method of improving dynamic reference tracking for flash memory unit | Darlene Hamilton, Eric M. Ajimine, Ming-Huei Shieh, Lee Cleveland, Edward Franklin Runnion +1 more | 2004-05-11 |
| 6735124 | Flash memory device having four-bit cells | Ashot Melik-Martirosian, Sameer Haddad | 2004-05-11 |
| 6693321 | Replacing layers of an intergate dielectric layer with high-K material for improved scalability | Wei Zheng, Arvind Halliyal | 2004-02-17 |
| 6653189 | Source side boron implant and drain side MDD implant for deep sub 0.18 micron flash memory | Sameer Haddad, Yue-Song He, Timothy Thurgate, Chi Chang, Ngaching Wong | 2003-11-25 |
| 6642573 | Use of high-K dielectric material in modified ONO structure for semiconductor devices | Arvind Halliyal, Mark T. Ramsbey, Wei Zhang, Fred Cheung | 2003-11-04 |
| 6639271 | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same | Wei Zheng, Nicholas H. Tripsas, Zoran Krivokapic, Jack F. Thomas, Mark T. Ramsbey | 2003-10-28 |
| 6639844 | Overerase correction method | Zhizheng Liu, Yi He | 2003-10-28 |
| 6593606 | Staggered bitline strapping of a non-volatile memory cell | Shane Hollmer, Pau-Ling Chen, Richard Fastow | 2003-07-15 |
| 6538270 | Staggered bitline strapping of a non-volatile memory cell | Shane Hollmer, Pau-Ling Chen, Richard Fastow | 2003-03-25 |