Issued Patents All Time
Showing 26–50 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7365389 | Memory cell having enhanced high-K dielectric | Joong S. Jeon, Wei Zheng, Meng Ding, Hidehiko Shiraiwa | 2008-04-29 |
| 7339222 | Method for determining wordline critical dimension in a memory array and related structure | Meng Ding, Hidehiko Shiraiwa | 2008-03-04 |
| 7303964 | Self-aligned STI SONOS | Hidehiko Shiraiwa, Yu Sun | 2007-12-04 |
| 7283402 | Methods and systems for high write performance in multi-bit flash memory devices | Darlene Hamilton, Roni Kornitz | 2007-10-16 |
| 7262095 | System and method for reducing process-induced charging | Ashot Melik Martirosian, Zhizheng Liu | 2007-08-28 |
| 7215577 | Flash memory cell and methods for programming and erasing | Zhizheng Liu, Zengtao T. Liu, Yi He | 2007-05-08 |
| 7206224 | Methods and systems for high write performance in multi-bit flash memory devices | Darlene Hamilton, Roni Kornitz | 2007-04-17 |
| 7176113 | LDC implant for mirrorbit to improve Vt roll-off and form sharper junction | Nga-Ching Wong, Weidong Qian, Sameer Haddad, Mark T. Ramsbey, Tazrien Kamal | 2007-02-13 |
| 7170796 | Methods and systems for reducing the threshold voltage distribution following a memory cell erase | Yi He, Gwyn Robert Jones, Edward Franklin Runnion | 2007-01-30 |
| 7167398 | System and method for erasing a memory cell | Zhizheng Liu, Satoshi Torii, Yi He | 2007-01-23 |
| 7160773 | Methods and apparatus for wordline protection in flash memory devices | — | 2007-01-09 |
| 7125763 | Silicided buried bitline process for a non-volatile memory cell | Daniel Sobek, Timothy Thurgate | 2006-10-24 |
| 7120063 | Flash memory cell and methods for programming and erasing | Zhizheng Liu, Zengtao T. Liu, Yi He | 2006-10-10 |
| 7071538 | One stack with steam oxide for charge retention | Hidehiko Shiraiwa, Harpreet Sachar, Wei Zheng | 2006-07-04 |
| 7001807 | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same | Wei Zheng, Nicholas H. Tripsas, Zoran Krivokapic, Jack F. Thomas, Mark T. Ramsbey | 2006-02-21 |
| 6967873 | Memory device and method using positive gate stress to recover overerased cell | Darlene Hamilton, Zhizheng Liu, Yi He, Edward Hsia, Kulachet Tanpairoj +2 more | 2005-11-22 |
| 6965143 | Recess channel flash architecture for reduced short channel effect | Wei Zheng | 2005-11-15 |
| 6958272 | Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell | Emmanuil H. Lingunis, Nga-Ching Wong, Sameer Haddad, Mark T. Ramsbey, Ashot Melik-Martirosian +2 more | 2005-10-25 |
| 6934190 | Ramp source hot-hole programming for trap based non-volatile memory devices | Zengtao T. Liu, Zhizheng Liu, Yi He, Sameer Haddad | 2005-08-23 |
| 6911704 | Memory cell array with staggered local inter-connect structure | Sameer Haddad, Timothy Thurgate, Richard Fastow | 2005-06-28 |
| 6906959 | Method and system for erasing a nitride memory device | Chi Chang, Yi He, Wei Zheng, Edward Franklin Runnion, Zhizheng Liu | 2005-06-14 |
| 6900085 | ESD implant following spacer deposition | Mark T. Ramsbey, Michael Fliesler, Mimi Qian, Yu Sun | 2005-05-31 |
| 6897110 | Method of protecting a memory array from charge damage during fabrication | Yi He, Wei Zheng, Zhizheng Liu, Darlene Hamilton, Ken Tanpairoj | 2005-05-24 |
| 6894932 | Dual cell memory device having a top dielectric stack | Ashot Melik-Martirosian, Sameer Haddad | 2005-05-17 |
| 6868014 | Memory device with reduced operating voltage having dielectric stack | Ashot Melik-Martirosian, Sameer Haddad | 2005-03-15 |