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USPTO Patent Rankings Data through Dec 31, 2025
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Pauling Chen — 9 Patents

AMD: 8 patents #1,554 of 9,280Top 20%
ETElite Semiconductor Memory Technology: 1 patents #42 of 77Top 55%
Saratoga, CA: #909 of 2,933 inventorsTop 35%
California: #67,547 of 386,348 inventorsTop 20%
Overall (All Time): #535,341 of 4,157,543Top 15%
9 Patents All Time
Pauling Chen has been granted 9 US patents while listed as an inventor at AMD. The first was granted in 2001 and the most recent in September 2021. Pauling Chen ranks #535,341 of 4,157,543 US inventors in our database (top 12.9%). Patent records list Pauling Chen in Saratoga, CA, US.

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11119854 Method of controlling verification operations for error correction of non-volatile memory device, and non-volatile memory device Yu-Kuo Yang, Takao Akaogi 2021-09-14
6885250 Cascode amplifier circuit for generating and maintaining a fast, stable and accurate bit line voltage Binh Quang Le, Lee Cleveland 2005-04-26 $7,241,000
6788583 Pre-charge method for reading a non-volatile memory cell Yi He, Edward Franklin Runnion, Zhizheng Liu, Mark Randolph, Darlene Hamilton +1 more 2004-09-07 $2,099,000
6771545 Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array Edward Hsia, Eric M. Ajimine, Darlene Hamilton, Ming-Huei Shieh, Mark Randolph +2 more 2004-08-03 $1,898,000
6768679 Selection circuit for accurate memory read operations Binh Quang Le, Michael Achter, Lee Cleveland 2004-07-27 $2,306,000
6768677 Cascode amplifier circuit for producing a fast, stable and accurate bit line voltage Binh Quang Le, Lee Cleveland 2004-07-27 $2,306,000
6744674 Circuit for fast and accurate memory read operations Binh Quang Le, Roger Tsao 2004-06-01 $2,717,000
6275424 Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device Binh Quang Le 2001-08-14 $3,163,000
6240017 Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device Binh Quang Le 2001-05-29 $6,079,000