Issued Patents All Time
Showing 76–97 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6762483 | Narrow fin FinFET | Zoran Krivokapic, Judy Xilin An, Srikanteswara Dakshina-Murthy, Bin Yu | 2004-07-13 |
| 6756276 | Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication | Qi Xiang, Jung-Suk Goo | 2004-06-29 |
| 6756643 | Dual silicon layer for chemical mechanical polishing planarization | Krishnashree Achuthan, Shibly S. Ahmed, Bin Yu | 2004-06-29 |
| 6730576 | Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer | Paul R. Besser, Jung-Suk Goo, Minh Van Ngo, Eric N. Paton, Qi Xiang | 2004-05-04 |
| 6716690 | Uniformly doped source/drain junction in a double-gate MOSFET | Judy Xilin An, Bin Yu | 2004-04-06 |
| 6709982 | Double spacer FinFET formation | Matthew S. Buynoski, Judy Xilin An, Bin Yu | 2004-03-23 |
| 6706571 | Method for forming multiple structures in a semiconductor device | Bin Yu, Judy Xilin An, Cyrus E. Tabery | 2004-03-16 |
| 6703648 | Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication | Qi Xiang, Eric N. Paton | 2004-03-09 |
| 6686231 | Damascene gate process with sacrificial oxide in semiconductor devices | Shibly S. Ahmed, Bin Yu | 2004-02-03 |
| 6680233 | Semiconductor device formed with disposable spacer and liner using high-K material and method of fabrication | Bin Yu, Qi Xiang | 2004-01-20 |
| 6660578 | High-K dielectric having barrier layer for P-doped devices and method of fabrication | Olov Karlsson, Qi Xiang, Bin Yu, Zoran Krivokapic | 2003-12-09 |
| 6657223 | Strained silicon MOSFET having silicon source/drain regions and method for its fabrication | Qi Xiang | 2003-12-02 |
| 6657276 | Shallow trench isolation (STI) region with high-K liner and method of formation | Olov Karlsson, Bin Yu, Zoran Krivokapic, Qi Xiang | 2003-12-02 |
| 6657267 | Semiconductor device and fabrication technique using a high-K liner for spacer etch stop | Qi Xiang, Olov Karlsson, Bin Yu | 2003-12-02 |
| 6645797 | Method for forming fins in a FinFET device using sacrificial carbon layer | Matthew S. Buynoski, Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Chih-Yuh Yang, Bin Yu | 2003-11-11 |
| 6630720 | Asymmetric semiconductor device having dual work function gate and method of fabrication | Witold P. Maszara, Qi Xiang | 2003-10-07 |
| 6620671 | Method of fabricating transistor having a single crystalline gate conductor | Joong S. Jeon | 2003-09-16 |
| 6611029 | Double gate semiconductor device having separate gates | Shibly S. Ahmed, Bin Yu | 2003-08-26 |
| 6586808 | Semiconductor device having multi-work function gate electrode and multi-segment gate dielectric | Qi Xiang, Witold P. Maszara | 2003-07-01 |
| 6528858 | MOSFETs with differing gate dielectrics and method of formation | Bin Yu, Qi Xiang, Olov Karlsson, Zoran Krivokapic | 2003-03-04 |
| 6465267 | Method of measuring gate capacitance to determine the electrical thickness of gate dielectrics | Qi Xiang | 2002-10-15 |
| 6448165 | Method for controlling the amount of trim of a gate structure of a field effect transistor | Bin Yu | 2002-09-10 |