Issued Patents All Time
Showing 26–50 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10193011 | Method of manufacturing a 3 color LED integrated Si CMOS driver wafer using die to wafer bonding approach | Srinivasa Banna, Luke England, Rahul Agarwal | 2019-01-29 |
| 10177178 | Assembly of CMOS driver wafer and LED wafer for microdisplay | Srinivasa Banna | 2019-01-08 |
| 10056453 | Semiconductor wafers with reduced bow and warpage | Ajey Poovannummoottil Jacob, Srinivasa Banna, Bartlomiej Jan Pawlak | 2018-08-21 |
| 10037981 | Integrated display system with multi-color light emitting diodes (LEDs) | Srinivasa Banna, Sanjay Jha, Ajey Poovannummoottil Jacob | 2018-07-31 |
| 9941330 | LEDs with three color RGB pixels for displays | Srinivasa Banna, Ajey Poovannummoottil Jacob | 2018-04-10 |
| 9941329 | Light emitting diodes (LEDs) with integrated CMOS circuits | Srinivasa Banna, Ajey Poovannummoottil Jacob | 2018-04-10 |
| 9748335 | Method, apparatus and system for improved nanowire/nanosheet spacers | Steven Bentley | 2017-08-29 |
| 9711511 | Vertical channel transistor-based semiconductor memory structure | Kwan-Yong Lim, Ryan Ryoung-Han Kim, Motoi Ichihashi, Youngtag Woo | 2017-07-18 |
| 9685529 | III-V NFETs including channel barrier layers to reduce band-to-band leakage current | Zoran Krivokapic, Srinivasa Banna | 2017-06-20 |
| 9406799 | High mobility PMOS and NMOS devices having Si—Ge quantum wells | — | 2016-08-02 |
| 8120075 | Semiconductor device with improved trenches | Yuhao Luo | 2012-02-21 |
| 7956385 | Circuit for protecting a transistor during the manufacture of an integrated circuit device | Yuhao Luo, Shuxian Wu, Xin Wu, Jae-Gyung Ahn, Daniel Gitlin | 2011-06-07 |
| 7936006 | Semiconductor device with backfilled isolation | Yuhao Luo, Daniel Gitlin | 2011-05-03 |
| 7875543 | Strain-silicon CMOS using etch-stop layer and method of manufacture | Yuhao Luo | 2011-01-25 |
| 7851313 | Semiconductor device and process for improved etch control of strained silicon alloy trenches | Yuhao Luo | 2010-12-14 |
| 7772093 | Method of and circuit for protecting a transistor formed on a die | Yuhao Luo, Shuxian Wu, Xin Wu, Jae-Gyung Ahn, Daniel Gitlin | 2010-08-10 |
| 7670923 | Method of fabricating strain-silicon CMOS | Yuhao Luo | 2010-03-02 |
| 7655991 | CMOS device with stressed sidewall spacers | Yuhao Luo | 2010-02-02 |
| 7429526 | Method of forming silicide gate with interlayer | Yuhao Luo | 2008-09-30 |
| 7429775 | Method of fabricating strain-silicon CMOS | Yuhao Luo | 2008-09-30 |
| 7423283 | Strain-silicon CMOS using etch-stop layer and method of manufacture | Yuhao Luo | 2008-09-09 |
| 7214629 | Strain-silicon CMOS with dual-stressed film | Yuhao Luo | 2007-05-08 |
| 6506640 | Multiple channel implantation to form retrograde channel profile and to engineer threshold voltage and sub-surface punch-through | Emi Ishida, Ming-Yin Hao | 2003-01-14 |
| 6372590 | Method for making transistor having reduced series resistance | Ming-Yin Hao | 2002-04-16 |
| 6194259 | Forming retrograde channel profile and shallow LLDD/S-D extensions using nitrogen implants | Ming-Yin Hao | 2001-02-27 |