Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431819 | Three-phase inverter and control method for same | Jian WU, Biaojie QI, Yongchun YANG | 2025-09-30 |
| 12424974 | Detection device for photovoltaic assembly | Dongming Zhou, Xuan ZHU | 2025-09-23 |
| 12413068 | Shutoff device and photovoltaic system | Dongming Zhou | 2025-09-09 |
| 12407172 | Current source response method and apparatus, and computer-readable storage medium | Kaifeng Jin, Dongming Zhou | 2025-09-02 |
| 11881813 | Module switchoff device and security protection system of photovoltaic power generation system | Dongming Zhou | 2024-01-23 |
| 11770065 | Control method and system for three-phase grid-connected inverter, and three-phase grid-connected inverter | Biaojie QI, Jian WU, Yongchun YANG | 2023-09-26 |
| 11695350 | Control method and system for three-phase grid-connected inverter, and three-phase grid-connected inverter | Jian WU, Biaojie QI, Yongchun YANG | 2023-07-04 |
| 9685781 | Solar photovoltaic system and a method for energy harvest optimization thereof and a method for fault detection thereof | Zhimin LING | 2017-06-20 |
| 9608447 | Solar photovoltaic three-phase micro-inverter and a solar photovoltaic generation system | — | 2017-03-28 |
| 9543854 | Solar photovoltaic three-phase micro-inverter system and a method for improving the conversion efficiency thereof | Dongming Zhou | 2017-01-10 |
| 9520721 | Solar photovoltaic three-phase micro-inverter and solar photovoltaic power generation system | — | 2016-12-13 |
| 8343795 | Method to break and assemble solar cells | Zhi-Min Ling | 2013-01-01 |
| 8120075 | Semiconductor device with improved trenches | Deepak Nayak | 2012-02-21 |
| 7956385 | Circuit for protecting a transistor during the manufacture of an integrated circuit device | Shuxian Wu, Xin Wu, Jae-Gyung Ahn, Deepak Nayak, Daniel Gitlin | 2011-06-07 |
| 7936006 | Semiconductor device with backfilled isolation | Deepak Nayak, Daniel Gitlin | 2011-05-03 |
| 7875543 | Strain-silicon CMOS using etch-stop layer and method of manufacture | Deepak Nayak | 2011-01-25 |
| 7851313 | Semiconductor device and process for improved etch control of strained silicon alloy trenches | Deepak Nayak | 2010-12-14 |
| 7772093 | Method of and circuit for protecting a transistor formed on a die | Shuxian Wu, Xin Wu, Jae-Gyung Ahn, Deepak Nayak, Daniel Gitlin | 2010-08-10 |
| 7670923 | Method of fabricating strain-silicon CMOS | Deepak Nayak | 2010-03-02 |
| 7673270 | Method and apparatus for compensating an integrated circuit layout for mechanical stress effects | Yan Wang, Nui Chong, Hong-Tsz Pan, Bang-Thu Nguyen, Jonathan Ho +4 more | 2010-03-02 |
| 7655991 | CMOS device with stressed sidewall spacers | Deepak Nayak | 2010-02-02 |
| 7635843 | In-line reliability test using E-beam scan | Jonathan Chang | 2009-12-22 |
| 7429526 | Method of forming silicide gate with interlayer | Deepak Nayak | 2008-09-30 |
| 7429775 | Method of fabricating strain-silicon CMOS | Deepak Nayak | 2008-09-30 |
| 7423283 | Strain-silicon CMOS using etch-stop layer and method of manufacture | Deepak Nayak | 2008-09-09 |