Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › CMOS device with stressed sidewall spacers

CMOS device with stressed sidewall spacers

US Patent 7655991 · Granted Feb 2, 2010

Estimated economic value: $11,045,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Three-phase inverter and control method for same2025
Detection device for photovoltaic assembly2025
Shutoff device and photovoltaic system2025
Current source response method and apparatus, and computer-readable storage medi2025
Beam and antenna array split configuration optimization2024
Systems and methods for managing online identity authentication risk in a nuance2024
Module switchoff device and security protection system of photovoltaic power gen2024
Method for determining beam interference2023
Control method and system for three-phase grid-connected inverter, and three-pha2023
Control method and system for three-phase grid-connected inverter, and three-pha2023
Method for beam selection and base station for implementing same2023
Object storage data storage systems and methods2023