Issued Patents All Time
Showing 26–50 of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7113431 | Quad bit using hot-hole erase for CBD control | Alykhan Madhani, Fatima Bathul, Satoshi Torii | 2006-09-26 |
| 7103706 | System and method for multi-bit flash reads using dual dynamic references | Michael A. Van Buskirk, Pua-Ling Chen, Kazuhiro Kuribara | 2006-09-05 |
| 7068204 | System that facilitates reading multi-level data in non-volatile memory | Fatima Bathul, Eugen Gershon | 2006-06-27 |
| 7038948 | Read approach for multi-level virtual ground memory | Fatima Bathul, Masato Horiike, Eugen Gershon, Michael Van Buskirk | 2006-05-02 |
| 7038950 | Multi bit program algorithm | Ed Hsia, Pau-Ling Chen | 2006-05-02 |
| 7023740 | Substrate bias for programming non-volatile memory | Nga-Ching Wong | 2006-04-04 |
| 7010736 | Address sequencer within BIST (Built-in-Self-Test) system | Boon Tang Teh, Edward V. Bautista, Jr., Ken Cheong Cheah, Colin S. Bill, Joseph Kucera +1 more | 2006-03-07 |
| 7009887 | Method of determining voltage compensation for flash memory devices | Ed Hsia, Alykhan Madhani, Kenneth K. Yu | 2006-03-07 |
| 6967873 | Memory device and method using positive gate stress to recover overerased cell | Zhizheng Liu, Mark Randolph, Yi He, Edward Hsia, Kulachet Tanpairoj +2 more | 2005-11-22 |
| 6956768 | Method of programming dual cell memory device to store multiple data states per cell | Kulachet Tanpairoj, Edward Hsia, Yi He | 2005-10-18 |
| 6944057 | Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference | Edward Franklin Runnion, Tien-Chun Yang, Binh Quang Le, Shigekazu Yamada, Ming-Huei Shieh +2 more | 2005-09-13 |
| 6901010 | Erase method for a dual bit memory cell | Eric M. Ajimine, Binh Quang Le, Edward Hsia, Ken Tanpairoj | 2005-05-31 |
| 6897110 | Method of protecting a memory array from charge damage during fabrication | Yi He, Wei Zheng, Zhizheng Liu, Mark Randolph, Ken Tanpairoj | 2005-05-24 |
| 6822909 | Method of controlling program threshold voltage distribution of a dual cell memory device | Edward Hsia, Mark Randolph, Edward Franklin Runnion, Kulachet Tanpairoj | 2004-11-23 |
| 6813752 | Method of determining charge loss activation energy of a memory array | Edward Hsia, Wei Zheng, Mark Randolph, Kulachet Tanpairoj | 2004-11-02 |
| 6799256 | System and method for multi-bit flash reads using dual dynamic references | Michael A. Van Buskirk, Pua-Ling Chen, Kazuhiro Kuribara | 2004-09-28 |
| 6791880 | Non-volatile memory read circuit with end of life simulation | Kazuhiro Kurihara, Binh Quang Le, Pau-Ling Chen, Edward Hsia | 2004-09-14 |
| 6788583 | Pre-charge method for reading a non-volatile memory cell | Yi He, Edward Franklin Runnion, Zhizheng Liu, Mark Randolph, Pauling Chen +1 more | 2004-09-07 |
| 6778442 | Method of dual cell memory device operation for improved end-of-life read margin | Edward Hsia, Kulachet Tanpairoj, Alykhan Madhani, Mimi Lee | 2004-08-17 |
| 6775187 | Method of programming a dual cell memory device | Edward Franklin Runnion, Edward Hsia, Kulachet Tanpairoj | 2004-08-10 |
| 6771545 | Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array | Edward Hsia, Eric M. Ajimine, Pauling Chen, Ming-Huei Shieh, Mark Randolph +2 more | 2004-08-03 |
| 6768673 | Method of programming and reading a dual cell memory device | Edward Hsia, Kulachet Tanpairoj, Mimi Lee, Alykhan Madhani, Yi He | 2004-07-27 |
| 6743677 | Method for fabricating nitride memory cells using a floating gate fabrication process | Mark Randolph, Binh Quang Le, Wei Zheng | 2004-06-01 |
| 6735114 | Method of improving dynamic reference tracking for flash memory unit | Eric M. Ajimine, Ming-Huei Shieh, Lee Cleveland, Edward Franklin Runnion, Mark Randolph +1 more | 2004-05-11 |
| 6707078 | Dummy wordline for erase and bitline leakage | Hidehiko Shiraiwa, Yider Wu, Jean Y. Yang, Mark T. Ramsbey | 2004-03-16 |