Issued Patents All Time
Showing 51–69 of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6631086 | On-chip repair of defective address of core flash memory cells | Colin S. Bill, Ken Cheong Cheah, Edward V. Bautista, Jr., Azrul Halim | 2003-10-07 |
| 6590811 | Higher program VT and faster programming rates based on improved erase methods | Narbeh Derhacobian, Janet Wang, Kulachet Tanpairoj | 2003-07-08 |
| 6579781 | Elimination of n+ contact implant from flash technologies by replacement with standard double-diffused and n+ implants | Len Toyoshiba | 2003-06-17 |
| 6567303 | Charge injection | Janet Wang, Narbeh Derhacobian, Tim Thurgate, Michael Han | 2003-05-20 |
| 6512701 | Erase method for dual bit virtual ground flash | Kulachet Tanpairoj, Yider Wu | 2003-01-28 |
| 6493266 | Soft program and soft program verify of the core cells in flash memory array | Santosh Yachareni, Binh Quang Le, Kazuhiro Kurihara | 2002-12-10 |
| 6493261 | Single bit array edges | Kulachet Tanpairoj, Ravi Sunkavalli, Narbeh Derhacobian, Michael A. Van Buskirk | 2002-12-10 |
| 6456533 | Higher program VT and faster programming rates based on improved erase methods | Narbeh Derhacobian, Janet Wang, Kulachet Tanpairoj | 2002-09-24 |
| 6440789 | Photoresist spacer process simplification to eliminate the standard polysilicon or oxide spacer process for flash memory circuits | Len Toyoshiba, Michael Fliesler | 2002-08-27 |
| 6442074 | Tailored erase method using higher program VT and higher negative gate erase | Kulachet Tanpairoj, Ravi Sunkavalli, Narbeh Derhacobian | 2002-08-27 |
| 6385093 | I/O partitioning system and methodology to reduce band-to-band tunneling current during erase | Edward V. Bautista, Jr., Kazuhiro Kurihara, Feng Pan, Weng Fook Lee, Ravi Sunkavalli | 2002-05-07 |
| 6381550 | Method of utilizing fast chip erase to screen endurance rejects | Edward Hsia, Phuong Banh | 2002-04-30 |
| 6344994 | Data retention characteristics as a result of high temperature bake | Yider Wu, Michael Han | 2002-02-05 |
| 6331951 | Method and system for embedded chip erase verification | Edward V. Bautista, Jr., Weng Fook Lee, Pau-Ling Chen, Keith H. Wong | 2001-12-18 |
| 6307784 | Negative gate erase | Narbeh Derhacobian, Kulachet Tanpairoj, Ravi Sunkavalli | 2001-10-23 |
| 6277690 | Elimination of N+ implant from flash technologies by replacement with standard medium-doped-drain (Mdd) implant | Len Toyoshiba | 2001-08-21 |
| 5818082 | E.sup.2 PROM device having erase gate in oxide isolation region in shallow trench and method of manufacture thereof | Hsingya Arthur Wang, Jein-Chen Young | 1998-10-06 |
| 5724365 | Method of utilizing redundancy testing to substitute for main array programming and AC speed reads | Edward Hsia, Jose Hernan Hernandez | 1998-03-03 |
| 5656521 | Method of erasing UPROM transistors | Issac H. Yamasaki | 1997-08-12 |