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First read countermeasures in memory |
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First read countermeasures in memory |
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Input of test conditions and output generation for built-in self test |
Mimi Lee, Darlene Hamilton |
2010-03-02 |
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Page—EXE erase algorithm for flash memory |
Mimi Lee, Darlene Hamilton |
2008-08-19 |
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Automated tests for built-in self test |
Mimi Lee, Darlene Hamilton, Kendra Nguyen, Xin Guo |
2007-10-16 |
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Flexible latency in flash memory |
Jih Hong Beh |
2007-01-02 |
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Diagnostic mode for testing functionality of BIST (built-in-self-test) back-end state machine |
Edward V. Bautista, Jr., Colin S. Bill |
2006-04-11 |
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Address sequencer within BIST (Built-in-Self-Test) system |
Boon Tang Teh, Edward V. Bautista, Jr., Colin S. Bill, Joseph Kucera, Weng Fook Lee +1 more |
2006-03-07 |
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Edward V. Bautista, Jr., Chi Mun Ho |
2005-12-27 |
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2005-12-06 |
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CAM (content addressable memory) cells as part of core array in flash memory device |
Edward V. Bautista, Jr. |
2005-11-29 |
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System and method for erase voltage control during multiple sector erase of a flash memory device |
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2005-05-10 |
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Implementing reference current measurement mode within reference array programming mode or reference array erase mode in a semiconductor |
Edward V. Bautista, Jr., Weng Fook Lee |
2004-08-03 |
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Generation of margining voltage on-chip during testing CAM portion of flash memory device |
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2004-03-16 |
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On-chip erase pulse counter for efficient erase verify BIST (built-in-self-test) mode |
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2003-12-16 |
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On-chip repair of defective address of core flash memory cells |
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2003-10-07 |
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Two-stage pipeline sensing for page mode flash memory |
— |
2001-06-05 |